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US 8,819,392 B2Granted
Providing metadata in a translation lookaside buffer (TLB)
AssigneeIntel Corporation
InventorsDavid Champagne, Abhishek Tiwari, Wei Wu, Christopher J. Hughes, Sanjeev Kumar, Shih-Lien Lu
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Abstract
In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.
Claims20
A processor comprising:
- a first core to execute instructions;
- and
- a first translation lookaside buffer (TLB) coupled to the first core, wherein the first TLB is to store a plurality of entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store a plurality of bits for a memory page of a main memory associated with the VA-to-PA translation, the plurality of bits to indicate at least one attribute of information in the memory page, wherein the main memory has a page frame storage area to store a plurality of page tables each having a plurality of page table entries each corresponding to a memory page and a second storage area separated in address space from the page frame storage area to store the plurality of bits for each of the page table entries, a first bit of the plurality of bits of a first state to indicate whether a corresponding memory page has been initialized.
A processor comprising:
- a first core to execute instructions;
- a first cache coupled to the first core to store attribute information for a memory page, the attribute information to be maintained coherent with a table stored in a memory that includes the attribute information, the attribute information including initialization information;
- a first miss handler logic to handle a miss to the first cache;
- a second core to execute instructions;
- and
- a second cache coupled to the second core to store attribute information for a memory page, the attribute information to be maintained coherent with the table stored in the memory, wherein the first core is to cause eviction of the attribute information stored in the second cache when an update to at least one bit of the attribute information in the first cache occurs.
3 more elements
A method comprising:
- storing, for each of a plurality of entries of a translation lookaside buffer (TLB), translation information for a memory page in a first portion of the TLB, each of the entries corresponding to a page table entry for a page frame stored in a page frame area of a main memory and storing attribute information for the memory page in a second portion of the TLB, the attribute information for each memory page obtained from a tag structure associated with the page frame and stored in a tag storage area present in a separate region of the main memory, the attribute information including initialization information for heap data;
- and
- generating an exception responsive to access to uninitialized heap data based on the attribute information.
Dependencies are inferred from the claim text.