Data processing apparatus and method for performing memory transactions within such a data processing apparatus

A data processing apparatus comprising:

• processing circuitry configured to execute a sequence of instructions including a memory access instruction, the processing circuitry including memory control circuitry configured to execute said memory access instruction to generate a memory transaction comprising at least one address transfer specifying a memory address and at least one associated data transfer specifying data to be accessed at the specified memory address;
• a first interface and a second interface;
• the memory control circuitry being configured to route each address transfer and associated data transfer via the first interface when the specified memory address is within a first memory address range, and to route each address transfer and associated data transfer via the second interface when the specified memory address is within a second memory address range;
• the memory control circuitry further being configured, when using the first interface, to execute the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the first interface with a first relative timing;
• and
• the memory control circuitry further being configured, when using the second interface, to modify execution of the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the second interface with a second relative timing different to said first relative timing, wherein the memory control circuitry comprises buffer circuitry selectively employed during modified execution of the memory access instruction to achieve the second relative timing of each address transfer and associated data transfer as presented at the second interface, wherein:
• the memory transaction is a read transaction causing data to be read from memory into at least one register of a register file accessible to the processing circuitry;
• the memory control circuitry is configured for at least one type of read transaction, when using the second interface, to buffer the data of each data transfer as received at the second interface within the buffer circuitry for at least one clock cycle if the register file is not available to receive that data transfer at that time, so as to allow each address transfer and associated data transfer to be presented at the second interface during the same clock cycle.

A method of performing memory transactions within a data processing apparatus comprising a first interface, a second interface, and processing circuitry for executing a sequence of instructions including a memory access instruction, the method comprising:

• employing memory control circuitry within the processing circuitry to execute the memory access instruction to generate a memory transaction comprising at least one address transfer specifying a memory address and at least one associated data transfer specifying data to be accessed at the specified memory address;
• routing each address transfer and associated data transfer via the first interface when the specified memory address is within a first memory address range, and routing each address transfer and associated data transfer via the second interface when the specified memory address is within a second memory address range;
• when using the first interface, arranging the memory control circuitry to execute the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the first interface with a first relative timing;
• and
• when using the second interface, arranging the memory control circuitry to modify execution of the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the second interface with a second relative timing different to said first relative timing;
• selectively employing buffer circuitry within the memory control circuitry during modified execution of the memory access instruction to achieve the second relative timing of each address transfer and associated data transfer as presented at the second interface;
• using an address generator within the memory control circuitry to generate the memory address for each address transfer;
• for at least one type of memory transaction, when using the second interface, buffering each memory address generated by the address generator within the buffer circuitry for at least one clock cycle, such that each address transfer and associated data transfer is presented at the second interface during the same clock cycle;
• and
• not buffering the memory address generated by the address generator if the memory transaction is a single-beat memory transaction comprising a single address transfer and an associated single data transfer.

A data processing apparatus comprising:

• processing means for executing a sequence of instructions including a memory access instruction, the processing means including memory control means for executing said memory access instruction to generate a memory transaction comprising at least one address transfer specifying a memory address and at least one associated data transfer specifying data to be accessed at the specified memory address;
• first interface means and second interface means;
• the memory control means for routing each address transfer and associated data transfer via the first interface means when the specified memory address is within a first memory address range, and for routing each address transfer and associated data transfer via the second interface means when the specified memory address is within a second memory address range;
• the memory control means for executing the memory access instruction, when using the first interface means, so as to cause each address transfer and associated data transfer to be presented at the first interface means with a first relative timing;
• and
• the memory control means further for modifying execution of the memory access instruction, when using the second interface means, so as to cause each address transfer and associated data transfer to be presented at the second interface means with a second relative timing different to said first relative timing;
• wherein the memory control means comprises buffer means selectively employed during modified execution of the memory access instruction for achieving the second relative timing of each address transfer and associated data transfer as presented at the second interface means;
• wherein:
• the memory control means includes an address generator means for generating the memory address for each address transfer;
• and
• the memory control means, for at least one type of memory transaction, when using the second interface means, for buffering each memory address generated by the address generator means within the buffer means for at least one clock cycle, such that each address transfer and associated data transfer is presented at the second interface means during the same clock cycle;
• wherein the memory control means does not buffer the memory address generated by the address generator means if the memory transaction is a single-beat memory transaction comprising a single address transfer and an associated single data transfer.