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US 8,819,354 B2Granted
Feedback programmable data strobe enable architecture for DDR memory applications
AssigneeLSI Corporation
InventorsHui-Yin Seto, Derrick Sai-Tang Butt, Cheng-Gang Kong
Life of this patent
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Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to read and write data through a plurality of input/output lines. The second circuit may include a plurality of sections. Each section may be configured to present a control signal to a load output line and receive a feedback of the control signal through a load input line. The load input line and the load output line of each of the sections may be connected to a load circuit configured to match a respective memory load connected to each of the plurality of input/output lines.
Claims20
An apparatus comprising:
- a first circuit configured to read data from and write data to an external memory device connected to a plurality of input/output (I/O) pins of said apparatus, said first circuit comprising a plurality of data path circuits, each data path circuit configured to (i) present a data strobe output signal to the external memory device via a respective one of said plurality of input/output (I/O) pins, (ii) receive a data strobe input signal from said external memory device via said respective one of said I/O pins, and (iii) gate a read data path in response to a respective gating control signal;
- and
- a second circuit comprising a plurality of feedback circuits, each feedback circuit corresponding to a respective one of said plurality of data path circuits and configured to (i) present a feedback control signal to a respective external load circuit connected to a respective load output pin of said apparatus, (ii) receive a feedback of said feedback control signal from said respective external load circuit through a respective load input pin of said apparatus, and (iii) generate the respective gating control signal for the respective data path circuit in response to the feedback received via the respective load input pin, wherein said respective external load circuit is configured to match a load of said external memory device connected to said plurality of input/output pins and said feedback circuits compensate for signal flight time variations between said apparatus and said external memory device.
An apparatus comprising:
- means for reading data from and writing data to an external memory device connected to a plurality of input/output (I/O) pins of said apparatus, said means for reading and writing comprising a plurality of means for providing a data path, each data path means configured to (i) present a data strobe output signal to a respective one of said plurality of input/output (I/O) pins, (ii) receive a data strobe input signal from said external memory device via the respective one of said I/O pins, and (iii) gate a read data path in response to a respective gating control signal;
- and
- means for implementing a plurality of feedback circuits, each feedback circuit corresponding to a respective one of said plurality of data path means and configured to (i) present a feedback control signal to a respective external load circuit connected to a respective load output pin of said apparatus, (ii) receive a feedback of said feedback control signal from said external load circuit through a respective load input pin of said apparatus, and (iii) generate the respective gating control signal for the respective data path means in response to the feedback received via the respective load input pin, wherein said respective external load circuit is configured to match a load of said external memory device connected to said plurality of input/output pins and said feedback circuits compensate for signal flight time variations between said apparatus and said external memory device.
A method for generating a programmable load signal comprising the steps of:
- (A) reading data from and writing data to an external memory connected to a plurality of input/output pins of an application specific integrated circuit (ASIC), wherein said plurality of input/output pins are connected to a plurality of data paths within said ASIC, each data path configured to (i) present a data strobe output signal to said external memory device via a respective one of said plurality of input/output (I/O) pins, (ii) receive a data strobe input signal from said external memory device via said respective one of said plurality of I/O pins and (iii) gate a read data path of each of said data paths in response to a respective gating control signal;
- and
- (B) implementing a plurality of feedback circuits, each feedback circuit corresponding to a respective one of said plurality of data paths and configured to present a feedback control signal to a respective external load circuit connected to a respective load output pin of said ASIC, receive a feedback of said feedback control signal from said external load circuit through a respective load input pin of said ASIC, and generate the respective gating control signal for the respective data path in response to the feedback received via the respective load input pin, wherein said respective external load circuit is configured to match a load of said memory connected to said plurality of input/output pins and one or more signal flight time variations between said ASIC and said external memory device are compensated.
Dependencies are inferred from the claim text.