Hybrid Transactional Memory (HybridTM)
AssigneeInternational Business Machines Corporation
InventorThomas J. Heller, Jr.
Life of this patent
Estimating the term…
Abstract
Embodiments related to a hardware transactional memory (HTM). An aspect includes setting a mode register of a processor core of a computer to indicate a HTM mode. Another aspect includes executing a plurality of transactions by the processor core in the HTM mode based on the mode register. Another aspect includes determining whether a first transaction of the plurality of transactions exceeds a failure limit of the processor core in the HTM mode. Yet another aspect includes, based on determining that the first transaction exceeds the failure limit of the processor core in the HTM mode, transitioning the processor to an assisted transaction mode by setting the mode register of the processor core to indicate the assisted transaction mode.
Claims20
A computer system for a hardware transactional memory (HTM), the system comprising:
- a processor core configured to:
- set a mode register of the processor core of a computer to indicate a HTM mode;
- execute a plurality of transactions by the processor core in the HTM mode based on the mode register;
- determine whether a first transaction of the plurality of transactions exceeds a failure limit of the processor core in the HTM mode;
- and
- based on determining that the first transaction exceeds the failure limit of the processor core in the HTM mode, transition the processor to an assisted transaction mode by setting the mode register of the processor core to indicate the assisted transaction mode.
A computer program product for a hardware transactional memory (HTM), the computer program product comprising a tangible, non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
- setting a mode register of a processor core of a computer to indicate a HTM mode;
- executing a plurality of transactions by the processor core in the HTM mode based on the mode register;
- determining whether a first transaction of the plurality of transactions exceeds a failure limit of the processor core in the HTM mode;
- based on determining that the first transaction exceeds the failure limit of the processor core in the HTM mode, transitioning the processor to an assisted transaction mode by setting the mode register of the processor core to indicate the assisted transaction mode.
A computer implemented method for a hardware transactional memory (HTM), comprising:
- setting a mode register of a processor core of a computer to indicate a HTM mode;
- executing a plurality of transactions by the processor core in the HTM mode based on the mode register;
- determining whether a first transaction of the plurality of transactions exceeds a failure limit of the processor core in the HTM mode;
- and
- based on determining that the first transaction exceeds the failure limit of the processor core in the HTM mode, transitioning the processor to an assisted transaction mode by setting the mode register of the processor core to indicate the assisted transaction mode.
Dependencies are inferred from the claim text.