Methods and apparatus for managing page crossing instructions with different cacheability

An apparatus for controlling execution of page crossing instructions with different cacheability, the apparatus comprising:

• an instruction cache configurable to store cacheable instructions and an instruction having a beginning portion that is cacheable and an ending portion that is non-cacheable and that crosses a cache line boundary at the end of a cache line;
• an indicator circuit configurable to store in one or more bits an indication that execution permission for the instruction is denied, wherein the instruction is identified as a non-cacheable instruction;
• and
• a fetch pipeline coupled to a processor and configurable to detect the indication when hitting on a fetch group of instructions that contains the non-cacheable instruction, wherein the non-cacheable instruction is received but not executed from the cache in response to the indication.

An apparatus for managing page crossing instructions with different cacheability, the apparatus comprising:

• an instruction cache configurable to store cacheable instructions and an instruction having a beginning portion that is cacheable and an ending portion that is non-cacheable and that crosses a page boundary and a cache line boundary at the end of a cache line:
• an indicator circuit configurable to store an indication that execution permission for the instruction is denied, wherein the instruction is identified as a non-cacheable instruction;
• and
• a fetch pipeline coupled to a processor and configurable to detect the indication when hitting on a fetch group of instructions that contains the non-cacheable instruction, wherein the non-cacheable instruction is refetched from system memory for execution bypassing the cache in response to the indication.

A computer readable non-transitory medium encoded with computer readable program data and code, the program data and code when executed operable to:

• set an indication for an ending portion of an instruction that was fetched from a first page of non-cacheable instructions and established with a beginning portion of the instruction that was fetched from a second page of cacheable instructions in a cache line having cacheable instructions, wherein the instruction crosses a cache line boundary;
• detect the indication in a fetch pipeline when hitting on the established cache line to set a non-cacheable flag to indicate that the instruction cannot be executed from the instruction cache, wherein the instruction is received but not executed from the cache based on the non-cacheable flag;
• and
• refetch at least the ending portion of the instruction from memory bypassing the cache in response to the non-cacheable flag to combine with the beginning portion of the instruction, wherein the instruction is reconstructed for execution.

An apparatus comprising:

• means for storing cacheable instructions and an instruction having a beginning portion that was fetched from a first page of cacheable instructions and an ending portion that was fetched from a second page of non-cacheable instructions and that crosses a cache line boundary at the end of a cache line;
• means for indicating that execution permission for the instruction is denied, wherein the instruction is identified as a non-cacheable instruction;
• and
• means for detecting the indication when hitting on a fetch group of instructions that contains the non-cacheable instruction, wherein the non-cacheable instruction is refetched from system memory for execution bypassing the cache in response to the indication.

An apparatus for controlling execution of page crossing instructions with different cacheability, the apparatus comprising:

• an instruction cache configurable to store cacheable instructions and an instruction having a beginning portion that is non-cacheable and an ending portion that is cacheable and that crosses a cache line boundary at the beginning of a cache line;
• an indicator circuit configurable to store in one or more bits an indication that execution permission for the instruction is denied, wherein the instruction is identified as a non-cacheable instruction;
• and
• a fetch pipeline coupled to a processor and configurable to detect the indication when hitting on a fetch group of instructions that contains the non-cacheable instruction, wherein the non-cacheable instruction is received but not executed from the cache in response to the indication.