System on chip comprising interconnector and control method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsJaegeun Yun, Sung-Min Hong, Bub-chul Jeong
Life of this patent
Estimating the term…
Abstract
A system on chip includes a plurality of master devices, a plurality of slave devices that supply data in response to requests of the plurality of master devices and pointer update logic configured to process the requests from the plurality of master devices sequentially in a pipeline manner.
Claims13
A system on chip comprising:
- a plurality of master devices;
- a plurality of slave devices configured to supply data in response to requests received from the plurality of master devices;
- and
- pointer update logic configured to process the requests of the plurality of master devices sequentially in a pipeline manner;
- wherein the pointer update logic comprises:
- a flip-flop configured to store a state of a handshake channel and to generate the state of the handshake channel at an output thereof;
- a temporal register configured to temporarily store a respective payload for each one of the requests;
- a register slice unit configured to store unique payloads for ones of the outstanding requests;
- update logic configured to transfer a payload stored in the temporal register to the register slice unit responsive to the state of the handshake channel output from the flip-flop;
- and
- a comparator configured to compare a payload corresponding to a currently input request with outstanding payloads stored in the temporal register and the register slice unit.
The system on chip of 1, wherein when a transaction ID of a payload stored in the temporal register is identical to one of transaction IDs of payloads stored in the register slice unit, the update logic updates state information for a payload stored in the register slice unit corresponding to the payload stored in the temporal register.
A system on chip, comprising:
- an interconnector circuit that is configured to manage the processing of requests between a plurality of master devices and a plurality of slave devices such that the requests from the plurality of master devices are transferred to the plurality of slave devices based on a comparison of a payload of a current one of the requests with payloads of previous ones of the requests;
- and
- a blocking circuit that is configured to block the transfer one of the requests from the plurality of master devices to the plurality of slave devices when the transaction identification of the one of the requests corresponds to a previous transaction identification having a request count and a response count associated therewith where the request count does not equal the response count;
- wherein each respective payload comprises a transaction identification and a direction associated with each respective request.
Dependencies are inferred from the claim text.