Low latency first-in-first-out (FIFO) buffer
AssigneeMarvell Israel (M.I.S.L) Ltd.
InventorsEvgeny Shumsky, Jonathan Kushnir
Life of this patent
Estimating the term…
Abstract
Systems and methods are provided for a first-in-first-out buffer. A buffer includes a first sub-buffer configured to store data received from a buffer input, and a second sub-buffer. The second sub-buffer is configured to store data received from either the buffer input or the first sub-buffer and to output data to a buffer output in a same order as that data is received at the buffer input. Buffer control logic is configured to selectively route data from the buffer input or the first sub-buffer to the second sub-buffer so that data received at the buffer input is available to be output from the second sub-buffer in a first-in-first-out manner.
Claims20
A buffer, comprising:
- a first sub-buffer configured to store data received from a buffer input;
- a second sub-buffer configured to store data received from both the buffer input and the first sub-buffer and to output data to a buffer output in a same order as that data is received at the buffer input, a latency of the second sub-buffer being less than a latency of the first sub-buffer, the second sub-buffer having exactly one memory location and being a pass-through buffer that bypasses the first sub-buffer that has a greater latency compared to the second sub-buffer;
- buffer control logic configured to selectively route data from the buffer input and the first sub-buffer to the second sub-buffer so that data received at the buffer input is available to be output from the second sub-buffer in a first-in-first-out manner,
- wherein the buffer control logic is configured to route data from the buffer input to the first sub-buffer when a data transmission rate of the buffer input keeps the first sub-buffer filled above a threshold level, wherein data is routed from the buffer input to the first sub-buffer at least one time, and
- wherein the buffer control logic is further configured to route data from the buffer input to the second sub-buffer, bypassing the first sub-buffer, when the data transmission rate fails to keep the first sub-buffer filled above the threshold level.
A method of buffering data, comprising:
- receiving input data at a buffer input;
- determining, using buffer control logic, a memory fullness/emptiness state of a first sub-buffer and of a second sub-buffer, wherein a latency of the second sub-buffer is less than a latency of the first sub-buffer, the second sub-buffer having exactly one memory location and being a pass-through buffer that bypasses the first sub-buffer that has a greater latency compared to the second sub-buffer;
- based on the memory fullness/emptiness states, selectively routing data from one of the buffer input and the first sub-buffer to the second sub-buffer so that data received at the buffer input is available to be output from the second sub-buffer in a first-in-first-out manner,
- wherein selectively routing includes:
- routing data from the buffer input to the first sub-buffer when a data transmission rate of the buffer input keeps the first sub-buffer filled above a threshold level, wherein data is routed from the buffer input to the first sub-buffer at least one time, and
- routing data from the buffer input to the second sub-buffer, bypassing the first sub-buffer, when the data transmission rate fails to keep the first sub-buffer filled above the threshold level.
Dependencies are inferred from the claim text.