Naming methodologies for a hierarchical system

#The present invention relates to the field of electronic design automation tools. In particular, the present invention relates to naming methodologies for a hierarchical system.

#An integrated circuit is a network of circuit elements such as resistors, capacitors, inductors, mutual inductors, transmission lines, diodes, bipolar junction transistors (BJT), junction field effect transistors (JFET), metal-oxide-semiconductor field effect transistors (MOSFET), metal-semiconductor field effect transistors (MESFET), thin-film transistors (TFT), etc.

#The development of complicated integrated circuits often requires the use of powerful numerical simulation programs. For example, circuit simulation is an essential part in the design flow of integrated circuits, helping circuit designers to verify the functionality and performance of their designs without going through expensive fabrication processes. As the semiconductor processing technology migrates to nanometer dimensions, new simulation methodologies are needed to solve the new problems intrinsically existing in circuit design with nanometer features. Modern integrated circuits continually challenge circuit simulation algorithms and implementations in the development of new technology generations. The semiconductor industry requires EDA software with the ability to analyze nanometer effects like coupling noise, ground bounce, transmission line wave propagation, dynamic leakage current, supply voltage drop, and nonlinear device and circuit behavior, which are all related to dynamic current. Thus, detailed circuit simulation and transistor-level simulation have become one of the most effective ways to investigate and resolve issues with nanometer designs.

#The aforementioned features and advantages of the invention, as well as additional features and advantages thereof, will be more clearly understandable after reading detailed descriptions of embodiments of the invention in conjunction with the following drawings.

#FIG. 1A illustrates a circuit that may be represented in a hierarchical system.

#FIG. 1B illustrates a hierarchical data structure that may be used in a hierarchical system.

#Naming methodologies for a hierarchical system are provided. The following descriptions are presented to enable any person skilled in the art to make and use the invention. Descriptions of specific embodiments and applications are provided only as examples. Various modifications and combinations of the examples described herein will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other examples and applications without departing from the spirit and scope of the invention. Thus, the present invention is not intended to be limited to the examples described and shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

#Some portions of the detailed description that follows are presented in terms of flowcharts, logic blocks, and other symbolic representations of operations on information that can be performed on a computer system. A procedure, computer-executed step, logic block, process, etc., is here conceived to be a self-consistent sequence of one or more steps or instructions leading to a desired result. The steps are those utilizing physical manipulations of physical quantities. These quantities can take the form of electrical, magnetic, or radio signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. These signals may be referred to at times as bits, values, elements, symbols, characters, terms, numbers, or the like. Each step may be performed by hardware, software, firmware, or combinations thereof.

#FIG. 2 illustrates a method of organizing instance names in a hierarchical system according to some aspects of the present disclosure. In the example shown in FIG. 2, the hierarchical system 200 includes two hierarchical levels, namely a top instance 202 and a plurality of leaf instances such as Leaf Instance 0 to Leaf Instance N (204a, 204b, . . . 204n). According to embodiments of the present disclosure, the hierarchical system may be represented in an instance name data structure. The top instance 202 includes a map of indexes 206 and a corresponding array of offsets 208. The hierarchical system further includes an Instance Name Table 210, which may be configured to store information of the instances in the hierarchical system.