Hardware description language (HDL) incorporating statistically derived data and related methods

A method for designing circuits, comprising:

• a) creating an initial HDL model of at least one circuit;
• a′) determining if the initial HDL model accurately matches desired behavior for the at least one circuit, and creating a new initial HDL model if the initial HDL model does not accurately match desired transistor level behavior;
• a″) establishing a plurality of variables for an algorithm for a parameter value, wherein the parameter value is derived from a design of experiments (DoE) statistical analysis performed on an initial design of the at least one circuit, and wherein the algorithm includes a multiple regression equation for generating the parameter value, wherein the multiple regression equation includes at least one term representing an interaction between the plurality of variables;
• b) creating an HDL model from the initial HDL model or the new HDL model for the at least one circuit, wherein the HDL model includes the algorithm for the parameter value;
• and
• c) executing a simulation of the at least one circuit with the HDL model for each of a plurality of corner conditions represented as different combinations of possible values for the plurality of variables.