Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-yeon Kim, Tae-hong Min, Yeong-kwon Ko, Tae-je Cho
Life of this patent
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Abstract
Semiconductor packages are disclosed. A semiconductor package includes: a first chip that includes a chip region and scribe regions at edges of the chip region, wherein the chip region comprises integrated circuit units and main through substrate vias electrically connected to the integrated circuit units; and a second chip that is bonded onto the first chip. The semiconductor package includes dummy conductive connectors including at least dummy wiring lines, the dummy conductive connectors electrically connected to the main through substrate vias at one end, and not capable of forming an electrical connection at the other end.
Claims20
A semiconductor package comprising:
- a first chip that includes a chip region and scribe regions at edges of the chip region, wherein the chip region comprises integrated circuit units and main through substrate vias electrically connected to the integrated circuit units;
- and
- a second chip that is bonded onto the first chip,
- wherein the semiconductor package includes dummy conductive connectors including at least dummy wiring lines, the dummy conductive connectors electrically connected to the main through substrate vias at one end, and arranged to prevent an electrical connection at the other end.
A semiconductor package comprising:
- a first chip that comprises through substrate vias connected to circuitry in the first chip, and first connection members that are electrically connected to the through substrate vias;
- a second chip that is stacked on the first chip and comprises second connection members that are electrically connected to the through substrate vias;
- and
- a sealing member that seals side surfaces of the first and second chip not to be exposed,
- wherein the first chip comprises dummy wiring lines that terminate at the side surfaces of the first chip and are electrically connected to the through substrate vias.
A semiconductor package, comprising:
- a first chip including through substrate vias electrically connected to circuitry within the first chip;
- first external connection terminals electrically connected to the through substrate vias, respectively;
- a second chip stacked on the first chip, the second chip including connection terminals electrically connected to the through substrate vias of the first chip;
- and
- a dummy conductive connector including at least a dummy wiring line, the dummy conductive connector including a first end electrically connected to the circuitry within the first chip and a second end left floating.
Dependencies are inferred from the claim text.