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US 8,811,531 B2Granted
Quadrature lattice matching network
AssigneeTriQuint Semiconductor, Inc.
InventorPeter V. Wright
Life of this patent
Estimating the term…
Abstract
Embodiments include but are not limited to apparatuses and systems including a quadrature lattice matching network including first path having a series inductor and a shunt inductor, and a second path having a series capacitor and a shunt capacitor. Other embodiments may be described and claimed.
Claims44
An apparatus comprising:
- a first power amplifier;
- a second power amplifier;
- a quadrature lattice matching network including a first path coupled with the first power amplifier and having a series inductor and a shunt inductor, and a second path coupled with the second power amplifier and having a series capacitor and a shunt capacitor;
- an output matching circuit including an output inductor coupled with an output capacitor and a load, wherein the output capacitor and the load are coupled in parallel, and wherein the output matching circuit is coupled with an output node of the quadrature lattice matching network;
- and
- a switch selectively coupling a first node, which is between the series inductor and the shunt inductor, with a second node, which is between the output inductor and the output capacitor.
3 more elements
An apparatus comprising:
- a first power amplifier;
- a second power amplifier;
- a quadrature lattice matching network including a first path coupled with the first power amplifier and having a series inductor and a shunt inductor, and a second path coupled with the second power amplifier and having a series capacitor and a shunt capacitor;
- an output matching circuit including an output inductor coupled with an output capacitor and a load, wherein the output capacitor and the load are coupled in parallel, and wherein the output matching circuit is coupled with an output node of the quadrature lattice matching network;
- and
- a first switch selectively coupling a first node, which is between the series inductor and the shunt inductor, with an output node of the quadrature lattice matching network.
3 more elements
An apparatus comprising:
- a first power amplifier;
- a second power amplifier;
- a quadrature lattice matching network including a first path coupled with the first power amplifier and having a series inductor and a shunt inductor, and a second path coupled with the second power amplifier and having a series capacitor and a shunt capacitor;
- an output matching circuit including an output inductor coupled with an output capacitor and a load, wherein the output capacitor and the load are coupled in parallel, and wherein the output matching circuit is coupled with an output node of the quadrature lattice matching network;
- and
- an output inductor coupled with an output node of the quadrature lattice matching network, an output capacitor coupled with the output inductor, and a third power amplifier coupled with a node between the output inductor and the output capacitor.
3 more elements
An apparatus comprising:
- a quadrature lattice matching network including a first path having a series inductor and a shunt inductor, a second path having a series capacitor and a shunt capacitor, and at least one switch operable to form a conductive path in parallel with at least one of the series inductor or the series capacitor;
- and
- a power amplifier coupled with the first path of the quadrature lattice matching network;
- wherein the switch is a first switch selectively coupling a first node, which is between the series inductor and the shunt inductor, with an output node of the quadrature lattice matching network.
1 more element
The apparatus of 15, further comprising a second switch selectively coupling a second node, which is between the series capacitor and the shunt capacitor, with the output node of the quadrature lattice matching network.
The apparatus of 15, further comprising a second switch selectively coupling the first node with a second node, which is between the series capacitor and the shunt capacitor.
An apparatus comprising:
- a quadrature lattice matching network including a first path having a series inductor and a shunt inductor, and a second path having a series capacitor and a shunt capacitor;
- a low-power amplifier coupled with the quadrature lattice matching network;
- and
- an output inductor coupled with an output node of the quadrature lattice matching network, and an output capacitor coupled in series with the output inductor, and wherein the low-power amplifier selectively coupled with a node between the output inductor and the output capacitor.
1 more element
An apparatus comprising:
- a first power amplifier;
- a second power amplifier;
- a quadrature combiner including a first path coupled with the first power amplifier, and a second path coupled with the second power amplifier;
- and
- a variable phase-modulation drive configured to drive the first power amplifier and the second power amplifier with a Ø of less than or greater than 180°;
- wherein the variable phase-modulation drive is configured to apply a change in Ø by equally shifting the drive to the first power amplifier and to the second power amplifier from a ر45° phase shift split.
3 more elements
A method comprising:
- controlling at least one power amplifier to provide a radio frequency (RF) signal to a quadrature lattice matching network including a first path located between a first power amplifier and a common output node and having a series inductor and a shunt inductor and a second path located between a second power amplifier and the common output node and having a series capacitor and a shunt capacitor;
- selectively coupling a first node between the series inductor and the shunt inductor with the output node of the quadrature lattice matching network;
- and
- transforming, by the quadrature lattice matching network, a source impedance associated with the at least one power amplifier to an output impedance at an output node of the quadrature lattice matching network.
1 more element
A method comprising:
- controlling a plurality of high-power amplifiers to provide a high-power radio frequency (RF) signal;
- transforming, with a quadrature lattice matching network including a first path having a series inductor and a shunt inductor, and a second path having a series capacitor and a shunt capacitor, a source impedance associated with the plurality of high-power amplifiers to an output impedance at an output node of the quadrature lattice matching network;
- and
- controlling a low-power amplifier directly coupled to the output node to provide a low-power RF signal to the output node of the quadrature lattice matching network.
1 more element
Dependencies are inferred from the claim text.