Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers

A hybrid bonding method for semiconductor wafers, the method comprising:

• providing a first semiconductor wafer and a second semiconductor wafer, the first semiconductor wafer and the second semiconductor wafer each having a plurality of conductive pads disposed within an insulating material on a top surface thereof;
• performing a chemical-mechanical polish (CMP) process on the top surfaces of the first semiconductor wafer and the second semiconductor wafer, wherein the CMP process forms recesses on top surfaces of the plurality of conductive pads;
• cleaning the top surfaces of the first semiconductor wafer and the second semiconductor wafer;
• forming a sealing layer over the top surfaces of the first semiconductor wafer and the second semiconductor wafer;
• removing the sealing layer from over the insulating material of the first semiconductor wafer and the second semiconductor wafer, leaving the sealing layer remaining in the recesses on the top surfaces of the plurality of conductive pads of the first semiconductor wafer and the second semiconductor wafer;
• coupling the top surface of the second semiconductor wafer to the top surface of the first semiconductor wafer;
• applying pressure to the first semiconductor wafer and the second semiconductor wafer to form a bond between the insulating materials of the first semiconductor wafer and the second semiconductor wafer;
• and
• heating the first semiconductor wafer and the second semiconductor wafer, wherein heating the first semiconductor wafer and the second semiconductor wafer forms a bond comprised of the sealing layer between the plurality of conductive pads of the first semiconductor wafer and the second semiconductor wafer.

A hybrid bonding method for semiconductor wafers, the method comprising:

• providing a first semiconductor wafer and a second semiconductor wafer, the first semiconductor wafer and the second semiconductor wafer each having a plurality of conductive pads disposed within an insulating material on a top surface thereof;
• forming a first layer of a sealing layer over the top surfaces of the first semiconductor wafer;
• forming a first layer of a sealing layer over the top surfaces of the second semiconductor wafer;
• forming a second layer of the sealing layer over the top surfaces of the first layer of the sealing layer on the first semiconductor wafer;
• forming a second layer of the sealing layer over the top surfaces of the first layer of the sealing layer on the second semiconductor wafer;
• removing the first layer of the sealing layer and the second layer of the sealing layer from over the insulating materials of the first semiconductor wafer and the second semiconductor wafer, respectively, leaving portions of the first layer of the sealing layer and the second layer of the sealing layer disposed over the respective plurality of conductive pads of the first semiconductor wafer and the second semiconductor wafer;
• coupling the top surface of the second semiconductor wafer to the top surface of the first semiconductor wafer;
• and
• applying heat and pressure to the first semiconductor wafer and the second semiconductor wafer, and forming a bond between the insulating material of the first semiconductor wafer and the insulating material of the second semiconductor wafers, and forming a bond comprising the sealing layer between the plurality of conductive pads of the first semiconductor wafer and the plurality of conductive pads of the second semiconductor wafer.