Controlling the access of master elements to slave elements over a communication bus

A method for controlling access of a plurality of master elements to one or more slave memory elements, comprising:

• receiving, by a central protection engine operably coupled to a communication bus and configured to control data flow between one or more slave elements and the plurality of master devices via the communication bus, an assignment of protection settings controlling access by the master devices to the slave devices;
• and
• checking, by the central protection engine whether a memory area of one of the one or more slave memory elements is inaccessible, wherein the checking comprises checking whether a RAM memory area of one of the one or more slave memory elements is configured as read only for all of the master elements, and thereby cannot be written to by any of the master elements.

A system comprising:

• one or more slave circuits operably coupled to a plurality of master devices, a central protection controller (CPC) operably coupled to a first communication bus and configured to control data flow between the one or more slave circuits and the plurality of master devices via the first communication bus and configured to protect access to memory of the one or more slave circuits during a supervisory mode of the system;
• and
• a Trusted Operating System (TOS) kernel, wherein the CPC is to allow the TOS kernel and associated device drivers to run with full access rights to the memory of the one or more slave circuits during the supervisory mode of the system and the CPC is to restrict access to the memory of the one or more slave circuits by invalidated software during the supervisory mode of the system.