Thread migration to improve power efficiency in a parallel processing environment
AssigneeIntel Corporation
InventorsQiong Cai, José González, Pedro Chappero Monferrer, Grigorios Magklis, Antonio González
Life of this patent
Estimating the term…
Abstract
A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.
Claims20
A method comprising:
- evaluating a plurality of threads being executed in parallel by a plurality of processing cores, the plurality of threads including a first thread and a second thread, the plurality of processing cores including a first processing core and a second processing core;
- based on the evaluating, detecting that a processing core executing the second thread is expected to wait idly for a completion of a task of the first thread, the detecting including comparing an amount of computing to be performed by the first thread with an amount of computing to be performed by the second thread;
- based on the detecting, determining with a processor and a memory a plan for improving a synchronization of the plurality of threads;
- and
- in response to determining the plan, generating a message identifying one of the plurality of threads as a thread to be moved from executing on the first processing core to executing on the second processing core.
A non-transitory computer readable storage medium having stored thereon instructions which when executed by one or more processors cause the one or more processors to perform a method comprising:
- evaluating a plurality of threads being executed in parallel by a plurality of processing cores, the plurality of threads including a first thread and a second thread, the plurality of processing cores including a first processing core and a second processing core;
- based on the evaluating, detecting that a processing core executing the second thread is expected to wait idly for a completion of a task of the first thread, the detecting including comparing an amount of computing to be performed by the first thread with an amount of computing to be performed by the second thread;
- based on the detecting, determining a plan for improving a synchronization of the plurality of threads;
- and
- in response to determining the plan, generating a message identifying one of the plurality of threads as a thread to be moved from executing on the first processing core to executing on the second processing core.
An apparatus comprising:
- an evaluation unit including hardware circuit logic to perform an evaluation of a plurality of threads being executed in parallel by a plurality of processing cores, the plurality of threads including a first thread and a second thread, the plurality of processing cores including a first processing core and a second processing core, the evaluation unit further to detect, based on the evaluation, that a processing core executing the second thread is expected to wait idly for a completion of a task of the first thread, wherein the evaluation unit to compare an amount of computing to be performed by the first thread with an amount of computing to be performed by the second thread;
- a synchronization calculator including hardware circuit logic to determine, based on the evaluation unit to detect that the processing core executing the second thread is expected to wait idly, a plan for improving a synchronization of the plurality of threads, the synchronization calculator further to generate, the synchronization calculator further to generate, based on the plan, a message to identify one of the plurality of threads as a thread to be moved from execution on the first processing core to execution on the second processing core.
Dependencies are inferred from the claim text.