Methods and apparatus for debugging programs in shared memory
AssigneeAnalog Devices, Inc.
InventorStephen M. Kilbane
Life of this patent
Estimating the term…
Abstract
A system debugging program code stored in shared memory and executed by multiple processors or processing cores. Exemplary operation includes determining if an address associated with an executing instruction is outside a first address range associated with the first processor, determining if the address associated with the executing instruction is outside a second address range associated with the second processor; and then raising an emulation event based on the first comparison but not the second comparison. Exemplary embodiments are also capable of identifying instructions corresponding to breakpoints which are executed by only one of multiple processors that execute program code stored in the shared memory.
Claims20
A method of debugging computer instructions, the method comprising:
- determining a plurality of instruction address ranges corresponding to regions of a first memory, the plurality of instruction address ranges including a first instruction address range and a second instruction address range;
- loading the first instruction address range into registers in a first processor to form a hardware breakpoint range;
- enabling a software breakpoint, in response to a determination that a current instruction address is not within the first instruction address range;
- and
- loading the second instruction address range into the registers from a second memory external to the first processor, in response to a determination that the current instruction address is within the second instruction address range.
A computing device, comprising:
- a memory having executable instructions stored therein;
- a debugging control unit;
- a plurality of instruction address ranges corresponding to regions of the memory, the plurality of instruction address ranges including a first instruction address range and a second instruction address range;
- and
- a first processor comprising
- (i) registers for storing the first instruction address range to form a hardware breakpoint range;
- and
- (ii) comparison logic that tests if a current instruction address is not within the first instruction address range,
- wherein the debugging control unit enables a software breakpoint, in response to a determination that the current instruction address is not within the first instruction address range, and supplies the second instruction address range from a memory in the debugging control unit to the first processor for storage in the registers, in response to a determination that the current instruction address is within the second instruction address range.
A debugging system, comprising:
- a first memory that stores a plurality of instruction address ranges corresponding to regions of a second memory based on addresses of executable instructions, the plurality of instruction address ranges including a first instruction address range and a second instruction address range, the first instruction address range stored into registers in a processor to form a hardware breakpoint range;
- and
- means for enabling a software breakpoint, in response to a determination that a current instruction address is not within the first instruction address range, wherein the second instruction address range is loaded into the registers from a memory external to the processor, in response to a determination that the current instruction address is within the second instruction address range.
Dependencies are inferred from the claim text.