Rule coverage rate auto-extraction and rule number auto-mark

A method for generating a photolithography mask, the method comprising:

• providing a computer program product having a non-transitory computer readable medium with a computer program embodied thereon, the computer program comprising a computer program code for:
• providing a target integrated circuit layout having a plurality of design rules associated therewith;
• performing a first design rule check on the target integrated circuit layout, wherein a first set of violations of the plurality of design rules and each design rule respectively associated with the first set of violations are recorded;
• performing a second design rule check on the target integrated circuit layout, wherein a second set of violations of the plurality of design rules and each design rule respectively associated with the second set violations are recorded;
• performing an analysis of the first set of violations, second set of violations, each design rule respectively associated with the first set of violations and second set of violations, and a frequency of usage of each of the plurality of design rules;
• determining a rule usage rate comprising a number of the frequency of usage of minimum rules used overall and a number of violations of each design rule respectively associated with the first set of violations and second set of violations;
• forming a rule database, wherein statistics associated with the rule usage rate are defined;
• replacing one or more of the design rules respectively associated with the first set of violations and second set of violations and one or more of the minimum rules with a standard rule based, at least in part, on the rule usage rate, therein defining a modified integrated circuit layout;
• and
• generating a photolithography mask based on the modified integrated circuit layout.

A computer program product for analyzing a design rule coverage rate, the computer program product having a non-transitory computer readable medium with a computer program embodied thereon, the computer program comprising a computer program code for:

• providing a target integrated circuit layout having a plurality of design rules associated therewith;
• performing a first design rule check on the target integrated circuit layout, wherein a first set of violations of the plurality of design rules and each design rule respectively associated with the first set of violations are recorded;
• performing a second design rule check on the target integrated circuit layout, wherein a second set of violations of the plurality of design rules and each design rule respectively associated with the second set violations are recorded;
• performing an analysis of the first set of violations, second set of violations, each design rule respectively associated with the first set of violations and second set of violations, and a frequency of usage of each of the plurality of design rules;
• determining a rule usage rate comprising an overall number of the frequency of usage of minimum rules used and a number of violations of each design rule respectively associated with the first set of violations and second set of violations;
• and
• forming an interactive rule database, wherein statistics associated with the rule usage rate are defined and utilized in subsequent implementation of the target integrated circuit layout.