Method and circuit to implement a static low power retention state
AssigneeQUALCOMM Incorporated
InventorsPatrick Chan, Rudolph Yeung
Life of this patent
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Abstract
An apparatus to pre-condition an operating integrated circuit (IC) device in a static low power retention state. The apparatus includes a pseudo random number generator that generates a pseudo random number value to pre-condition the static low power retention state of the operating IC device. The apparatus also includes a controller that drives the pseudo random number value into a test scan chain linking logic elements of the operating IC device responsive to the operating IC device entering a sleep mode. Driving the pseudo random number value into the test scan chain by the controller places the operating IC device into the static low power retention state.
Claims20
A method for preconditioning an operating integrated circuit (IC) device in a static low power retention state, comprising:
- generating a pseudo random number value using a pseudo random number generator to pre-condition the static low power retention state of the operating IC device;
- and
- driving the pseudo random number value into a test scan chain linking logic elements of the operating IC device responsive to the operating IC device entering a sleep mode, the pseudo random number value placing the operating IC device into the static low power retention state.
An apparatus to pre-condition an operating integrated circuit (IC) device in a static low power retention state, comprising:
- a pseudo random number generator configured to generate a pseudo random number value to pre-condition the static low power retention state of the operating IC device;
- and
- a controller configured to drive the pseudo random number value into a test scan chain linking logic elements of the operating IC device responsive to the operating IC device entering a sleep mode, the pseudo random number value placing the operating IC device into the static low power retention state.
An apparatus to pre-condition an operating integrated circuit (IC) device in a static low power retention state, comprising:
- a means for generating a pseudo random number value to pre-condition the static low power retention state of the operating IC device;
- and
- a means for driving the pseudo random number value into a test scan chain linking logic elements of the operating IC device responsive to the operating IC device entering a sleep mode, the pseudo random number value placing the operating IC device into the static low power retention state.
Dependencies are inferred from the claim text.