Method and system for layout parasitic estimation

A method comprising:

• providing a previously verified integrated circuit (IC) design implemented at a first technology node and having routing paths, the IC design to be ported to a second technology node being different from the first technology node;
• using an electronic design automation (EDA) tool to compute estimated parasitic capacitances of the routing paths of the previously verified IC design using a technology file associated with the second technology node;
• and
• estimating parasitic capacitances using a shrink factor based on the first and second technology nodes, wherein the step of using the EDA tool to compute estimated parasitic capacitances includes:
• accessing a table stored in a non-transitory, machine readable storage medium, the table containing a plurality of previously computed parasitic capacitance values corresponding to respective combinations of line length, line width and line spacing.

A non-transitory, computer readable storage medium encoded with computer program instructions, such that when the computer program instructions are executed by a computer, the computer acts as a special purpose processor for performing a method comprising:

• (a) generating a layout of an integrated circuit (IC) design using an electronic design automation (EDA) tool, the layout having a network of routing paths connecting at least two active layer devices of the IC design;
• (b) computing estimated parasitic capacitances of the routing paths of the network;
• (c) performing a first device level simulation of the network based on the at least two active layer devices and the estimated parasitic capacitances;
• (d) using the EDA tool to revise the layout or a device of the IC design if a result of the first device level simulation fails to satisfy an IC specification;
• wherein steps (b), (c) and (d) are performed one or more times before performing design rule checks and before performing layout-versus-schematic checks, until a result of the first device level simulation satisfies the IC specification;
• and
• (e) outputting the revised layout of the IC design to a non-transitory, machine readable storage medium after completion of steps (b) to (d), to be accessed by the EDA tool to perform design verification.

A system comprising:

• an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout;
• at least one non-transitory, computer readable storage medium, for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design;
• an RC tool for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and before performing design rule checks and before performing layout-versus-schematic checks, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC;
• and
• a first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.