Gradient AOCV methodology enabling graph-based timing closure with AOCV timing models
AssigneeTexas Instruments Incorporated
InventorsRaashid Moin Shaikh, Vishnuraj Arukat Rajan
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Abstract
A method of manufacturing semiconductor circuits seeks timing closure on a preliminarily select, placed and routed set of cells using a delay for each cell as derated by a derate value obtained from a timing model table having a derate value corresponding to a circuit path depth in the netlist. The derate value for a predetermined number of circuit path depths below k are identical. The derate values are monotonically decreasing for increasing circuit depths in a range between 1.0 and 1.5. Separate timing model tables with differing identical values can be employed for standard and clock tree cells.
Claims15
A method of manufacturing semiconductor circuits comprising the steps of:
- preliminarily selecting a set of cells to implement a circuit design expressed as a netlist;
- preliminarily placing said set of cells in positions corresponding to the netlist;
- preliminarily routing connections between said set of cells corresponding to the netlist;
- determining whether said preliminarily selected, placed and routed set of cells achieves timing closure using a delay for each cell of said set of cells as derated by a derate value obtained from a timing model table having a derate value corresponding to a circuit path depth in the netlist, said derate value for a predetermined number of circuit path depths below k being identical;
- repeating said steps of preliminarily selecting, preliminarily placing, preliminarily routing and determining until timing closure is achieved;
- and
- constructing a circuit in a semiconductor having cells selected, placed and routed to achieve timing closure.
A method of designing semiconductor circuits comprising the steps of:
- preliminarily selecting a set of cells to implement a circuit design expressed as a netlist;
- preliminarily placing said set of cells in positions corresponding to the netlist;
- preliminarily routing connections between said set of cells corresponding to the netlist;
- determining whether said preliminarily selected, placed and routed set of cells achieves timing closure employing an electronic design automation tool using a delay for each cell of said set of cells as derated by a derate value obtained from a timing model table having a derate value corresponding to a circuit path depth in the netlist, said derate value for a predetermined number of circuit path depths below k being identical;
- repeating said steps of preliminarily selecting, preliminarily placing, preliminarily routing and determining until timing closure is achieved.
Dependencies are inferred from the claim text.