Multiple-instantiated-module (MIM) aware pin assignment

A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for performing multiple-instantiated-module (MIM) aware pin assignment, the method comprising:

• determining an aggregate boundary-wire-length cost based on multiple boundary-wire-length costs corresponding to multiple instances of an MIM in a circuit design layout, wherein the MIM is a module that is instantiated at multiple locations in the circuit design layout;
• routing a net for one of the instances of the MIM to obtain a routed net, wherein said routing tries to minimize a routing cost function that includes the aggregate boundary-wire-length cost;
• determining a pin location for a pin based on the routed net;
• and
• placing the pin at the pin location in the multiple instances of the MIM.

A method for performing multiple-instantiated-module (MIM) aware pin assignment, the method comprising:

• determining an initial set of pin-alignment constraints in a circuit design layout;
• propagating, by computer, the initial set of pin-alignment constraints through one or more instances of one or more MIMs in the circuit design layout, wherein the MIM is a module that is instantiated at multiple locations in the circuit design layout;
• and
• performing pin assignment on MIMs in decreasing order of the number of pin-alignment constraints that are imposed on the MIMs.

An apparatus, comprising:

• a processor;
• and
• a non-transitory storage medium storing instructions that, when executed by the processor, cause the apparatus to perform a method for performing multiple-instantiated-module (MIM) aware pin assignment, the method comprising:
• determining an aggregate boundary-wire-length cost based on multiple boundary-wire-length costs corresponding to multiple instances of a MIM in a circuit design layout, wherein the MIM is a module that is instantiated at multiple locations in the circuit design layout;
• routing a net for one of the instances of the MIM to obtain a routed net, wherein said routing tries to minimize a routing cost function that includes the aggregate boundary-wire-length cost;
• determining a pin location for a pin based on the routed net;
• and
• placing the pin at the pin location in the multiple instances of the MIM.

A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for performing multiple-instantiated-module (MIM) aware pin assignment, the method comprising:

• determining an initial set of pin-alignment constraints in a circuit design layout;
• propagating the initial set of pin-alignment constraints through one or more instances of one or more MIMs in the circuit design layout, wherein the MIM is a module that is instantiated at multiple locations in the circuit design layout;
• and
• performing pin assignment on MIMs in decreasing order of the number of pin-alignment constraints that are imposed on the MIMs.

An apparatus, comprising:

• a processor;
• and
• a non-transitory storage medium storing instructions that, when executed by the processor, cause the apparatus to perform a method for performing multiple-instantiated-module (MIM) aware pin assignment, the method comprising:
• determining an initial set of pin-alignment constraints in a circuit design layout;
• propagating the initial set of pin-alignment constraints through one or more instances of one or more MIMs in the circuit design layout, wherein the MIM is a module that is instantiated at multiple locations in the circuit design layout;
• and
• performing pin assignment on MIMs in decreasing order of the number of pin-alignment constraints that are imposed on the MIMs.