US 8,806,395 B1 · Porting a circuit design from a first semiconductor process to a second semiconductor process

Abstract

Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated. Porting includes determining processing targets for the second semiconductor manufacturing process.

Claims20

Dependent claims

A method of fabricating an integrated circuit including a bit cell comprising:

determining a size of each transistor in a first bit cell design, each of the transistors having a threshold voltage;
producing a second bit cell design based on the first bit cell design, the second bit cell design having target transistors, the target transistors including at least one deeply depleted channel (DDC) transistor, the second bit cell design having initial threshold voltage value assigned to each of the target transistors;
determining targets for a read margin, a write margin, a read current and a cell leakage for the second bit cell, such targets defining set of design constraints;
optimizing the threshold voltage values of the target transistors using an optimization method based upon solving objective functions within the set of design constraints;
selectively doping a semiconductor substrate to form a highly-doped screening region over which a transistor gate will be formed;
selectively doping the semiconductor substrate in regions that are associated with the target transistors to dopant concentrations that set the threshold voltage values for each of the target transistors to the desired range of values;
and
forming a substantially undoped semiconductor layer above the highly doped screening region.

5 more elements

Dependencies are inferred from the claim text.

Porting a circuit design from a first semiconductor process to a second semiconductor process

Life of this patent

Porting a circuit design from a first semiconductor process to a second semiconductor process

Life of this patent

Abstract

Claims20