Distinguishable IC patterns with encoded information

An integrated circuit (IC) layout comprising a plurality of resembling patterns, each of the patterns comprising,

• a plurality of dummy features arrayed in a substantially regular fashion, each dummy feature having an identical set of observable parameters, each observable parameter having a numerical value, the plurality of dummy features comprising:
• an anchor group of anchor dummy features, wherein in all the patterns, any two correspondingly situated anchor dummy features share a common set of the numerical values with respect to the observable parameters thereof;
• and
• one or more tunable dummy features, each of the tunable dummy features having a fixed predetermined spatial relationship with the anchor group of anchor dummy features,
• wherein the tunable dummy features in each of the patterns have unique sets of the numerical values with respect to the observable parameters thereof such that any two of the patterns can be distinguished by their respective tunable dummy features.

A method comprising:

• receiving an integrated circuit design layout in a computer-readable medium, wherein the integrated circuit design layout includes a plurality of patterns, each of the patterns includes an anchor group of dummy features and a set of at least one tunable dummy feature that has a fixed predetermined spatial relationship with the anchor group, the anchor group of each of the patterns has a predetermined configuration, size, and location thereof, the anchor group is identical in each of the patterns, and the set of at least one tunable dummy feature is different in each of the patterns;
• receiving image information of a first pattern to be located in the IC design layout;
• determining, from the image information, a first anchor group of dummy features of the first pattern based on the predetermined configuration, size, and location;
• determining, from the image information, a first set of at least one tunable dummy feature of the first pattern based on the fixed predetermined spatial relationship with the first anchor group;
• and
• using a computer, locating one of the plurality of patterns in the integrated circuit design layout by matching the set of at least one tunable dummy feature of the one of the plurality of patterns to the first set.