Customized patterning modulation and optimization
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYing-Chou Cheng, Ru-Gun Liu, Josh J. H. Feng, Tsong-Hua Ou, Luke Lo, Chih-Ming Lai, Wen-Chun Huang
Life of this patent
Estimating the term…
Abstract
The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout.
Claims22
An integrated circuit (IC) design method comprising:
- providing an IC design layout of a circuit having a geometrical parameter;
- determining an electrical parameter of the integrated circuit based on the geometrical parameter of the IC design layout by accessing an electrical patterning (ePatterning) database and without simulating the IC design layout;
- applying an ePatterning modification to the IC design layout, by accessing the ePatterning database, to achieve a target electrical parameter of the integrated circuit and a target optical parameter of the IC design layout, wherein the ePatterning database associates the ePatterning modification with the target electrical parameter;
- and
- thereafter fabricating a mask according to the modified IC design layout.
An integrated circuit (IC) design method comprising:
- providing an IC design layout of an integrated circuit having a geometrical pattern;
- providing an ePatterning database associating the geometrical parameter of the IC design layout to both an electrical parameter of the integrated circuit and an optical parameter of the IC design layout;
- determining an electrical parameter and an optical parameter of the integrated circuit by accessing the ePatterning database and without simulating the IC design layout;
- extracting a change to the geometrical parameter from the ePatterning database according to a target electrical parameter of the integrated circuit and a target optical parameter the IC design layout, the ePatterning database associating the change to the geometrical parameter with the target electrical parameter of the integrated circuit;
- applying the change to the geometrical parameter of the IC design layout;
- and
- thereafter making a mask according to the changed IC design layout.
A method for making an integrated circuit (IC), comprising:
- providing an IC design layout by an IC designer, the IC design layout having a geometrical parameter;
- determining an electrical parameter of the integrated circuit based on the geometrical parameter of the IC design layout by accessing an electrical patterning (ePatterning) database and without simulating the IC design layout;
- adding an assistant feature to the IC design layout, by accessing the ePatterning database, in order for the electrical parameter of the integrated circuit to meet a specified electrical range made by a semiconductor manufacturer, wherein the ePatterning database associates the assistant feature with the specified electrical range;
- thereafter making a mask according to the IC design layout by the semiconductor manufacturer;
- and
- making a semiconductor wafer using the mask by the semiconductor manufacturer.
Dependencies are inferred from the claim text.