Fault position determining circuit, storage device and information processing apparatus
AssigneeFujitsu Limited
InventorTakahito Hirano
Life of this patent
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Abstract
A fault analyzing circuit has: a comparing circuit to compare fault data stored in a storage area with a fault being caused with data of an alternation register; and a position identifying circuit to identify an error bit position from data of a comparative result of the comparing circuit.
Claims6
A fault position determining circuit connected to a storage unit and an alternation register to retain, when a fault occurs in a storage area in the storage unit to which data is written, the data by way of an alternation area of the storage area, the circuit comprising:
- a comparing circuit to compare fault data stored in the storage area having the fault with the data retained in the alternation register;
- and
- a position identifying circuit to identify a fault bit position of the fault data on the basis of a comparative result of the comparing circuit.
A storage device comprising:
- a storage unit;
- an alternation register to retain, when a fault occurs in a storage area to which data is written in the storage unit, the data by way of an alternation area of the storage area;
- a comparing circuit to compare fault data stored in the storage area having the fault with the data retained in the alternation register;
- and
- a position identifying circuit to identify an error bit position from data of a comparative result of the comparing circuit.
An information processing apparatus comprising:
- a storage device;
- and
- a processing unit to process data stored in the storage device,
- the storage device including:
- a storage unit;
- an alternation register to retain, when a fault occurs in a storage area to which data is written in the storage unit, the data by way of an alternation area of the storage area;
- a comparing circuit to compare fault data stored in the storage area having the fault with the data retained in the alternation register;
- and
- a position identifying circuit to identify an error bit position from data of a comparative result of the comparing circuit.
Dependencies are inferred from the claim text.