Circuits, integrated circuits, and methods for interleaved parity computation

An integrated circuit, comprising:

• a first parity check circuit comprising a first input latch coupled to a first parity generator, the first parity generator also coupled to a first asynchronous latch and to a first synchronous latch, the first parity generator configured to check the parity of a first command/address word and provide a first result to the first asynchronous latch and the first synchronous latch;
• a second parity check circuit comprising a second input latch coupled to a second parity generator, the second parity generator also coupled to a second asynchronous latch and a second synchronous latch, the second parity generator configured to check the parity of a second command/address word and provide a second result to the second asynchronous latch and the second synchronous latch;
• a first logic circuit coupled to the first and second parity check circuits, configured to combine a first output from the first asynchronous latch and a second output from the second asynchronous latch and provide an asynchronous alert signal in response to the first and second outputs;
• and
• a second logic circuit also coupled to the first and second parity check circuits, configured to combine a third output from the first synchronous latch and a fourth output from the second synchronous latch and provide a synchronous parity error signal in response to the third and fourth outputs,
• wherein the first output is based at least in part on the first result and the second output is based at least in part on the second result.

A method, comprising:

• receiving a first set of bits at a first parity circuit during a first clock cycle, the first set of bits including a first parity bit;
• checking the parity of the first set of bits in the first parity circuit to determine whether the first set of bits was transmitted correctly;
• outputting a first result of the checking the parity of the first set of bits as a first output signal;
• receiving a second set of bits at a second parity circuit during a second clock cycle, the second set of bits including a second parity bit, and the second clock cycle being after the first clock cycle;
• checking the parity of the second set of bits in the second parity circuit to determine whether the second set of bits was transmitted correctly;
• and
• outputting a second result of the checking the parity of the second set of bits as a second output signal.

An interleaved parity computation circuit, comprising:

• a first parity circuit configured to receive a first set of bits including a first parity bit during a first clock cycle and generate a first synchronous signal indicative of the parity of the first set of bits, the first parity circuit including a first input latch coupled to a first a first generator, the first parity generator coupled to a first synchronous latch configured to provide the first synchronous signal, the first parity generator configured to check the parity of the first set of bits and provide a first result to the first synchronous latch;
• a second parity circuit distinct from the first parity circuit and configured to receive a second set of bits including a second parity bit during a second clock cycle and generate a second synchronous signal indicative of the parity of the second set of bits, the second parity circuit including a second input latch coupled to a second parity generator, the second parity generator coupled to a second synchronous latch configured to provide the second synchronous signal, the second parity generator configured to check the parity of the second set of bits and provide a second result to the second synchronous latch;
• and
• a combining circuit coupled to the first and second parity circuits and configured to provide a parity error signal indicative of whether the parity of at least one of the first and second set of bits was incorrect, the parity error signal selectively based on the first and second synchronous signals.