Reliability, availability, and serviceability in a memory device

A method comprising:

• reading data bits from a first portion of a memory core, the memory core comprising at least one split bank pair that has the first portion in a first memory bank and the second portion a second memory bank;
• reading stored error correction code (ECC) bits from a second portion of the memory core, wherein, in error check mode, data bits are stored in the first memory bank and corresponding error check bits are stored in the second memory bank, the memory core to support either error check mode or non-error check mode in response to a register bit;
• generating computed ECC bits using ECC computation logic, wherein the memory core and the ECC computation logic are on a common integrated circuit;
• and
• comparing the stored ECC bits with the computed ECC bits to determine whether the stored ECC bits match the computed ECC bits.

A system comprising:

• a dynamic random access memory (DRAM) device including
• a split bank pair of memory banks including a first memory bank and a second memory bank, wherein data bits are to be stored in the first memory bank and corresponding error correction code (ECC) bits (stored ECC bits) are to be stored in the second memory bank, if the DRAM device is in an error check mode, the DRAM device to support either error check mode or non-error check mode in response to a register bit, and
• error correction logic on the same die as the split bank pair, the error correction logic including ECC generation logic to compute ECC bits (computed ECC bits) corresponding to the data bits;
• and
• a requestor coupled with the DRAM device.