Error detection within a memory

A method for error detection in a memory, the method comprising:

• receiving an access to a memory, wherein the access comprises a request tag;
• determining a request parity based on the request tag;
• retrieving a stored tag and a stored parity associated with the request tag;
• determining an error correction status based on the stored tag and the stored parity associated with the request tag;
• determining a parity hotness by comparing the request parity and the stored parity;
• determining a tag hotness by comparing the request tag and the stored tag;
• and
• determining an error status associated with the access based on the parity hotness, the tag hotness and the error correction status.

A cache system including error detection, the cache system comprising:

• an error detection code encoder configured to determine a request parity based on a request tag received at a cache in association with an access;
• a tag memory operating in parallel with the error detection code encoder and configured to receive the request tag and determine a stored tag and a stored parity, wherein the tag memory and the error detection code encoder are configured to operate in parallel;
• ECC detection logic coupled to the tag memory and configured to receive the stored tag and the stored parity, determine an error correction status based on the stored tag and the stored parity and provide the error correction status on a single error flag line and a double error flag line;
• hotness logic coupled to the error detection code encoder and the ECC detection logic, wherein the hotness logic is operating in parallel with the ECC detection logic and configured to receive the stored tag and the stored parity, receive the request tag, receive the request parity from the error detection code encoder, determine a parity hotness by comparing the stored parity and the request parity and determine a tag hotness by comparing the stored tag and the request tag, provide the tag hotness on a tag match line, a tag one-hot line and a tag two-hot line, and provide the parity hotness on a parity match line, a parity one-hot line and a parity two-hot line;
• and
• error status logic coupled to the hotness logic and the ECC detection logic and configured to receive the parity hotness, the tag hotness and an error correction status, and determine an error status based on the parity hotness, tag hotness, and the error correction status, wherein the error status is provided on a double error status line, a HIT/MISS line and a fault line, wherein the HIT/MISS line is set to indicate that the requested tag is located in the memory, the double bit status error line is set to indicate that a double bit error was detected with respect to the access and a fault value is set to indicate that a detected double bit error cannot be corrected.