Dynamically allocatable memory error mitigation

A system comprising:

• a display;
• a memory coupled with a processor, the memory comprising multiple groups of memory units;
• a memory controller coupled with the memory, the memory controller to apply an error mitigation mechanism to one of multiple groups of memory units and deactivate a second group of the multiple groups of memory units, wherein the one group is in active use during an error test of a second group of memory units;
• and
• a test engine to test the second group of memory units for errors,
• wherein in response to detecting an error in a memory unit of the second group, the memory controller is to apply, to the memory unit of the second group having the error, the error mitigation mechanism for active use and activate the second group of memory units with the error mitigation mechanism applied to the memory unit of the second group having the error.

An apparatus comprising:

• a memory controller to couple with a memory having multiple groups of memory units, the memory controller to apply an error mitigation mechanism to one of the multiple groups of memory units and deactivate a second of the multiple groups of memory units, and wherein the one group of memory units is to be in active use during an error test of the second group of memory units;
• and
• a test engine to test the second group of memory units for errors,
• wherein in response to detecting an error in a memory unit of the second group, the memory controller is to apply, to the memory unit of the second group having the error, the error mitigation mechanism for active use and activate the second group of memory units with the error mitigation mechanism applied to the memory unit of the second group having the error.