US 8,806,284 B2 · Method for bit-error rate testing of resistance-based RAM cells using a reflected signal

Abstract

A testing method is described for performing a fast bit-error rate (BER) measurement on resistance-based RAM cells, such MTJ cells, at the wafer or chip level. Embodiments use one or more specially designed test memory cells fabricated with direct electrical connections between the two electrodes of the cell and external contact pads (or points) on the surface of the wafer (or chip). In the test setup the memory cell is connected an impedance mismatched transmission line through a probe for un-buffered, fast switching of the cell between the high and low resistance states without the need for CMOS logic to select and drive the cell. The unbalanced transmission line is used generate signal reflections from the cell that are a function of the resistance state. The reflected signal is used to detect whether the test cell has switched as expected.

Claims20

Dependent claims

A method for testing a memory cell, the memory cell having a low resistance state and a high resistance state that can be switched by predetermined voltage pulses applied to the memory cell, the method comprising:

connecting a test system to the memory cell, an impedance of the test system presented to the memory cell being unequal to an impedance of the memory cell when a selected test signal is applied;
applying the selected test signal to the memory cell, the selected test signal including a repeating cycle of voltage pulses selected to cause repetitive switching between the low resistance state and the high resistance state and to cause a reflected signal from the memory cell back to the test system, the reflected signal varying in an expected pattern when the memory cell switches between the low resistance state and the high resistance state;
and
detecting a switching error when the reflected signal differs from the expected pattern.

1 more element

An apparatus for testing a memory cell having a low resistance state and a high resistance state that can be switched by positive and negative voltage pulses applied to the memory cell, comprising:

a probe for making electrical connections to the memory cell and presenting an impedance to the memory cell selected to cause signal reflections from the memory cell when a selected test signal is applied to the memory cell through the probe;
a transmission line connected to the probe;
a test signal generator for applying the selected test signal to the memory cell through the transmission line connected to the probe, the test signal including a repeating cycle of voltage pulses that includes at least a positive pulse and a negative pulse selected to cause the memory cell to repeatedly switch between the low resistance state and the high resistance state and to cause signal reflections from the memory cell on the transmission line in a predetermined pattern that is a function of a resistance state of the memory cell;
and
switching error detection means for detecting switching errors when the signal reflections from the memory cell deviate from the predetermined pattern.

2 more elements

Dependencies are inferred from the claim text.

Method for bit-error rate testing of resistance-based RAM cells using a reflected signal

Life of this patent

Method for bit-error rate testing of resistance-based RAM cells using a reflected signal

Life of this patent

Abstract

Claims20