Skew management in an interconnection system
AssigneeViolin Memory, Inc.
InventorJon Bennett
Life of this patent
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Abstract
An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.
Claims19
An interconnect system, comprising:
- a plurality of active nodes;
- a bus having a plurality of signal lines connecting an adjacent pair of active nodes of the plurality of nodes;
- and
- wherein a first data bit on a first signal line of the plurality of signal lines and a second data bit on a second signal line of the plurality of signal lines are exchanged between the first signal line and the second signal line at a first active node of the pair of adjacent active nodes;
- wherein the first data bit having a first cumulative time delay at the first active node is exchanged with the second data bit having a second cumulative time delay at the first active node, so as to change a differential time delay between the first data bit and the second data bit at a second active node of the pair of adjacent active nodes, and the first active node is a transmitter of data and the second active node is a receiver of data.
An interconnect system, comprising:
- a plurality of nodes, each node of the plurality of nodes having an active electronic circuit configurable to exchange signals between two or more output terminals of the node, the active nodes connected to a bus;
- and
- a bus having a plurality of signal lines connecting the output terminals of a first node and input terminals of a second node of the plurality of nodes, the first and the second nodes on the bus;
- wherein a first data bit having a first cumulative time delay at the first node is exchanged with a second data bit having a second cumulative time delay at the first node, so as to change a differential time delay between the first cumulative time delay of the first data bit at the second node and the second cumulative time delay of the second data bit at the second node, and the first node transmits the first and the second data bits and the second node receives the first and the second data bits.
A computer program product stored on a non-transient computer readable medium having:
- instructions for configuring an active node of an interconnection system comprising active nodes connected by signal lines to:
- exchange a first data bit on a first signal line of the plurality of signal lines of a first active node and a second data bit on a second signal line of the plurality of signal lines of a first active node between the first signal line and the second signal line,
- wherein the first data bit having a first cumulative time delay at the first active node is exchanged with the second data bit having a second cumulative time delay at the first active node, so as to change a differential time delay between the first data bit and the second data bit at a second active node of a pair of active nodes, and the first active node is a transmitter of data and the second active node is a receiver of data.
Dependencies are inferred from the claim text.