Time division multiplexed multiport memory implemented using single-port memory elements

A method for operating a dual-port memory having first and second ports, wherein the dual-port memory includes an array of single-port memory elements, the method comprising:

• receiving a first memory access request and an associated first clock signal at the first port;
• receiving a second memory access request and an associated second clock signal at the second port;
• in response to the first clock signal going high, temporarily storing the first memory access request in a buffer;
• and
• in response to detecting a rising clock edge in the second clock signal with a control circuit, servicing the second memory access request while the first memory access request is stored in the buffer.

A dual-port memory having first and second ports comprising:

• an array of single-port memory elements;
• a first input latch operable to receive a first memory access request and a first clock signal associated with the first port;
• a second input latch operable to receive a second memory access request and a second clock signal associated with the second port, wherein the second clock signal is different than the first clock signal;
• a control circuit operable to receive the second clock signal and not the first clock signal, wherein the control circuit is further operable to generate a control signal that determines which one of the first and second memory access request is to be selected for fulfillment;
• and
• a multiplexing circuit having a first input operable to receive the first memory access request from the first input latch, a second input operable to receive the second memory access request from the second input latch, and a control input operable to receive the control signal from the control circuit.