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US 8,806,249 B1Granted
Systems and methods for reducing static and total power consumption in programmable logic device architectures
AssigneeAltera Corporation
InventorDavid Mendel
Life of this patent
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Abstract
A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the synthesis, placement, routing, and period following routing of the programmable logic device.
Claims21
A programmable logic device including a heterogeneous routing pool, the pool comprising:
- areas of low-power logic signal routing;
- and
- areas of high-power logic signal routing;
- wherein:
- the power consumption of each of the areas is taken into account in designating one of the areas for portions of a logic design to be programmed.
2 more elements
A heterogeneous routing pool for a programmable logic device, the heterogeneous routing pool comprising:
- areas of low-power logic signal routing;
- and
- areas of high-power logic signal routing;
- wherein:
- the power consumption of each of the areas is taken into account in designating one of the areas for portions of a logic design to be programmed.
2 more elements
Dependencies are inferred from the claim text.