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US 8,806,245 B2Granted
Memory read timing margin adjustment for a plurality of memory arrays according to predefined delay tables
AssigneeApple Inc.
InventorsErik P. Machnicki, Michael Frank
Life of this patent
Estimating the term…
Abstract
An apparatus and method for changing the extra margin adjustment (EMA) for a memory is disclosed. A control unit may access a table responsive to an indication of a change of operating point. The table includes a number of different delay times, each of which corresponds to a particular operating point. The control unit may select the delay time that corresponds to the new operating point to which the memory operation is being changed. The control unit may further convey an indication of the selected delay time to the memory, thereby causing the memory to operate according thereto.
Claims19
An integrated circuit comprising:
- a plurality of memory arrays;
- and
- a control unit coupled to the plurality of memory arrays, wherein the control unit includes a first table storing predefined delay values for a first one of the plurality of memory arrays, wherein each of the delay values is indicative of a delay time between the beginning of a read cycle and enabling of the first memory to provide valid data, wherein each delay value corresponds to a unique one of a plurality of predefined operating points;
- wherein responsive to an indication of a change of operation to a new operating point of the plurality of predefined operating points, the control unit is configured to access the first table to determine a first delay value based on a new value of the operating point and further configured to set the first delay value for the first memory array responsive to determining the first delay value;
- wherein the operating point includes a supply voltage used to power each of the plurality of memory arrays;
- and
- wherein the control unit further includes a second table storing delay values for each of the operating points for a second memory array, wherein responsive to an indication of a change of operation to a new value of the operating point, the control unit is configured to access the second table to determine a second delay value based on a new value of the operating point and further configured to set the second delay value for at least one of the second memory array responsive to determining the given delay value.
4 more elements
A method comprising:
- providing, to a control unit, an indication of a change of operation of an integrated circuit (IC) from a current operating point to a new operating point;
- responsive to the indication, the control unit accessing first and second tables respectively associated with first and second memories located on the IC, the first and second tables each storing a plurality of predefined delay values each corresponding to a unique one of a plurality of predefined operating points including the current operating point and the new operating point, wherein each of the delay values indicates a delay time between a start of a read cycle and a time when its respective memory is capable of outputting valid data, wherein each of the predefined operating points includes a supply voltage used to power the memory;
- the control unit selecting from each of the first and second tables respective delay values corresponding to the new operating point;
- and
- the control unit setting the first and second memories to operate at the selected respective delay values.
2 more elements
A method comprising:
- providing, to a power management unit, a request to operate a plurality of on-chip memories at a new value of a supply voltage, wherein the supply voltage is used to power the on-chip memories;
- the power management unit accessing a plurality of tables storing predefined delay values for each of a plurality of different supply voltages, each of the plurality of tables corresponding to a unique one of the plurality of memories, wherein each delay value indicates an amount of time required for sense amplifiers of the corresponding memory to provide valid data after assertion of word lines during a read cycle;
- the power management unit selecting delay values from each of the plurality of tables that correspond to the new value of the supply voltage;
- and
- the power management unit causing each of the plurality of memories to operate according to their respectively selected delay values.
2 more elements
An integrated circuit comprising:
- a plurality of memory arrays each powered by a supply voltage;
- and
- a power controller including a plurality of tables each storing a corresponding plurality of predefined delay times for a corresponding unique one of the plurality of memory arrays, wherein each of the delay times corresponds to one of a plurality of supply voltage values, wherein each of the delay times is indicative of a timing margin required for performing a memory access;
- wherein the power controller is configured to access the plurality of tables responsive to receiving an indication of a change of the supply voltage to a new value, wherein accessing the plurality of tables includes, for each of the plurality of memory arrays, selecting a respective delay time corresponding to the new value of the supply voltage;
- and
- wherein the power controller is further configured to provide the selected delay times to the respective ones of the plurality of memory arrays in order to cause the memory arrays to operate according to their newly selected delay times.
3 more elements
Dependencies are inferred from the claim text.