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AssigneeCanon Kabushiki Kaisha
InventorsKoji Shimizu, Kohei Asano, So Yokomizo
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In an information processing apparatus which incorporates a plurality of arithmetic units and a plurality of storage units, power consumption in a power saving mode is reduced, and a return time required to return from the power saving mode to a normal power mode is shortened. With this invention, in an information processing method in an information processing apparatus which incorporates a plurality of CPUs and a plurality of RAMs, when a condition required to transit to the power saving mode is satisfied, each CPU stores information associated with an operation state of an active program in one RAM, and turns off the power supply to devices except for the one RAM.
An information processing apparatus having a first power mode and a second power mode in which consumption power is lower than consumption power in the first power mode, comprising:
An information processing method in an information processing apparatus, which has a first power mode and a second power mode in which consumption power is lower than consumption power in the first power mode, wherein the information processing apparatus comprises a nonvolatile program storage unit configured to store a first program and a second program, both the first program and the second program being executed in the first power mode, a first arithmetic unit configured to execute, in the first power mode, the first program which is loaded to a first storage unit from the nonvolatile program storage unit, and a second arithmetic unit configured to execute, in the first power mode, the second program which is loaded to a volatile second storage unit from the nonvolatile program storage unit, the method comprising:
Dependencies are inferred from the claim text.