Systems and method for hardware dynamic cache power management via bridge and power manager

A method comprising:

• detecting that a cache is to be powered up in a system including one or more processors coupled to the cache, wherein the one or more processors are powered down at a time of the detecting;
• issuing a request to a bridge that is coupled to the cache and one or more peripherals, wherein the bridge is configured to bridge memory operations issued by each of the one or more peripherals through the cache to a memory controller, and wherein the bridge is configured to bridge operations from the processors to the peripherals, and wherein the peripherals comprise one or more hardware input/output (I/O) devices, and wherein the bridge is coupled to the cache via a separate connection than a connection of the memory controller to the cache, and wherein the bridge is configured to couple to one or more peripherals via a second separate connection than the separate connection of the bridge to the cache;
• the bridge responding to the request by performing a plurality of operations stored in the bridge to initialize one or more configuration registers in the cache;
• detecting that the cache is to be powered down in a power manager, wherein the detecting is responsive to detecting that the one or more processors are powered down and further responsive to detecting that there are no pending operations from the one or more peripherals to the memory controller;
• issuing a second request to the bridge indicating that the cache is to be powered down;
• and
• the bridge responding to the second request by performing one or more second operations stored in the bridge, wherein the one or more second operations include a first write operation to a first configuration register in the cache, wherein the first write operation causes the cache to perform a command.

A system comprising:

• one or more processors;
• a cache coupled to the one or more processors, the cache comprising a plurality of configuration registers that are programmable to control operation of the cache;
• a memory controller coupled to the cache;
• a power manager coupled to the processors and the cache, wherein the power manager is configured to control power up and power down of the processors and the cache;
• and
• a bridge coupled to the cache via a separate connection than a connection of the memory controller to the cache, and wherein the bridge is coupled to the power manager, and wherein the bridge is configured to couple to one or more peripherals via a second separate connection than the separate connection of the bridge to the cache, and wherein the bridge is configured to bridge memory operations issued by each of the one or more peripherals through the cache to a memory controller, and wherein the bridge is configured to bridge operations from the processors to the peripherals, and wherein the peripherals comprise one or more hardware input/output (I/O) devices, and wherein the bridge comprises a plurality of registers programmable with address and data pairs representing register writes to the plurality of configuration registers, and wherein the bridge is configured to perform at least a first register write to a first configuration register of the plurality of configuration registers in response to a power down event for the cache signalled by the power manager, wherein the first register write causes the cache to perform a command, and wherein the bridge is configured to perform at least a second register write to a second configuration register of the plurality of configuration registers in response to a power up event for the cache, and wherein the power manager configured to generate the power down event responsive to detecting that the one or more processors are powered down and further responsive to detecting that there are no pending operations from the one or more peripherals to the memory controller.