Prefetch engine based translation prefetching

A system for translation prefetching, comprising:

• a main processor;
• a main memory;
• one or more cache memory;
• a prefetch engine logically located between a cache hierarchy of the main processor and the main memory and operable to receive instructions to prefetch data from the main memory, the prefetch engine incorporated with a system memory controller of the main processor, the data for prefetching being data that is anticipated for future access by the main processor and prefetching of the data to be performed prior to when the data is needed, the prefetch engine further operable to search one or more cache translation entries for a mapping of a virtual address corresponding to the prefetch data to a physical address, the prefetch engine further operable to perform address mapping translation translating the virtual address of the data to be prefetched to a physical address without interrupting the main processor and without direct operating system service, if there is no virtual to physical address mapping found in the one or more cache translation entries, the prefetch engine further operable to prefetch the data and store the translated address mapping in the one or more cache memory, if there is no virtual to physical address mapping found in the one or more cache translation entries, wherein the prefetch engine is enabled to store data directly to selected levels of the main processor's cache hierarchy and maintain cache coherency of the main processor's cache hierarchy.

A system for translation prefetching, comprising:

• a main processor;
• a prefetch engine logically located between a cache hierarchy of the main processor and a main memory, the prefetch engine incorporated with a system memory controller of the main processor, and operable to at least carry out one or more instructions to prefetch data for the main processor to use, the data for prefetching being data that is anticipated for future access by the main processor and prefetching of the data to be performed prior to when the data is needed, the prefetch engine further operable to at least tag a prefetch request for unmapped data to be prefetched that does not have a virtual address to a physical address mapping cached in an address translation cache;
• and
• an interrupt vector dedicated to unmapped prefetch requests,
• wherein the interrupt vector is generated when a prefetch is to unmapped data, and in response to the interrupt vector, unmapped data's address is translated and the unmapped data is prefetched into a cache location without interrupting the main processor and without direct operating system service, and the unmapped data's address translation is stored in a respective cache translation buffer, wherein the prefetch engine is enabled to store data directly to selected levels of the main processor's cache hierarchy and maintain cache coherency of the main processor's cache hierarchy;
• a first level translation look aside table and a second level translation look aside table located in the main processor's cache hierarchy wherein the first level translation look aside table is stored in smaller and higher speed memory than the second level translation look aside table, and wherein prefetch engine's pre-load page table entries are stored in the second level translation look aside table.