Methods and apparatuses for improving speculation success in processors
AssigneeOracle America, Inc.
InventorsZoran Radovic, Erik Martin Roland Karlsson
Life of this patent
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Abstract
Methods and apparatuses are disclosed for improving speculation success in processors. In some embodiments, the method may include executing a plurality of threads of program code, the plurality of threads comprising a first speculative load request, setting an indicator bit corresponding to a cache line in response to the first speculative load request, and in the event that a second speculative load request from the plurality of threads refers to a first cache line with the indicator bit set, determining if a second cache line is available.
Claims20
A method of executing instructions in a computer system, the method comprising the acts of:
- increasing an overall processing speed of at least one processor core by utilizing idle time of the at least one processor core to perform speculative execution on a program code by:
- executing, using the at least one processor core, a plurality of threads of program code, the plurality of threads comprising a first speculative load request;
- setting a first indicator bit corresponding to a first cache line in response to the first speculative load request;
- in the event that a second speculative load request from the plurality of threads refers to the first cache line with the first indicator bit set, executing a first cache replacement scheme to determine if a second cache line is available that does not have a second indicator bit set, the second indicator bit corresponding to the second cache line;
- in the event that the second cache line is not available, reattempting to identify the second cache line for a number of times;
- and
- after the number of times, executing a second cache replacement scheme to determine if a third cache line is available.
A computer system comprising:
- a plurality of processing cores, each capable of executing at least one thread of program code;
- a cache coupled to the plurality of processing cores, wherein each cache line within the cache further comprises an indicator bit;
- increasing an overall processing speed of one or more of the plurality of processor cores by utilizing idle time of the one or more of the plurality of processing cores to perform speculative execution on a program code by:
- executing a first thread of the program code and a second thread of the program code out of order;
- in the event that a load request from the second thread hits to a first cache line with a first indicator bit set, the one or more of the plurality of processing cores executes a first cache replacement scheme to determine if a second cache line is available that does not have a second indicator bit set and wherein the second thread continues to execute the program code out-of-order;
- in the event that the second cache line is not available, reattempting to identify the second cache line for a number of times;
- and
- after the number of times, executing a second cache replacement scheme to determine if a third cache line is available.
A non-transitory tangible storage medium comprising instructions capable of being executed by a computer system, the instructions comprising the acts of:
- increasing an overall processing speed of at least one processor core by utilizing idle time of the at least one processor core to perform speculative execution on a program code by:
- speculatively executing a first thread of the program code while a second thread of the program code is executing;
- and
- in the event that the speculative data access conflicts, executing a first cache replacement scheme to determine a second cache line without a conflict by:
- determining if an indicator bit corresponding to the second cache line is not set;
- in the event that the second cache line is not available, reattemptinq to identify the second cache line for a number of times;
- and
- after the number of times, executing a second cache replacement scheme to determine if a third cache line is available.
Dependencies are inferred from the claim text.