List based prefetch

A system for increasing performance in a parallel computing system, the system comprising:

• a hardware prefetch engine prefetching data, from a memory storage device, whose addresses appear in a list while the parallel computing system processing source code, the list describing an arbitrary sequence of prior cache miss addresses;
• a compiler controlling the prefetching of the data by using at least one compiler directive;
• the hardware prefetch engine storing current cache miss addresses in a queue, creating the list based on the stored current cache miss addresses, and using the list at a next processing of the source code;
• the hardware prefetch engine detecting a new cache miss, comparing an address corresponding to the detected new cache miss against a predetermined number of the current cache miss addresses stored in the queue, identifying a match between the compared address and one of the stored addresses in the queue, indicating that a portion of a lower-level cache line is missed upon identifying the match, and moving an address at a head of the queue from the queue to an array upon identifying no match.

A computer program product for increasing performance in a parallel computing system, the computer program product comprising a non-transitory storage medium readable by a processing circuit and storing instructions run by the processing circuit for performing a method, the method comprising:

• while processing source code, prefetching data, from a memory storage device, whose addresses appear in a list, the list describing an arbitrary sequence of prior cache miss addresses;
• and
• controlling the prefetching of the data by using at least one compiler directive issued by a compiler,
• wherein parallel computing system consumes the prior cache miss addresses in the list at a rate of one prior cache miss address every one or more clock cycles, and the parallel computing system, including the compiler, estimates a maximum prefetch depth that is needed to ensure that the prefetched data become available when a prior cache miss address in the list turns out as a current cache miss address.