Cache replacement using active cache line counters

A method for performing data caching, the method comprising the steps of:

• receiving a main memory address for accessing requested data in a corresponding location in main memory, the main memory being organized into a plurality of segments, at least a portion of the memory address including a segment identifier referencing one of the plurality of segments;
• comparing segment identifiers corresponding to the plurality of segments in a segment memory with the segment identifier in the received main memory address for determining whether there is a segment match;
• for each of at least a subset of the plurality of segments, tracking a number of active cache lines in a cache memory associated with a corresponding one of the segments;
• and
• when a segment match has not occurred and the cache memory is full, implementing a cache segment replacement policy based at least on information relating to the number of active cache lines associated with the corresponding one of the segments.

An electronic system, comprising:

• at least one apparatus for performing data caching, the at least one apparatus comprising:
• at least one cache memory including a plurality of cache lines arranged into a plurality of segments, each segment having a subset of the cache lines associated therewith;
• a first plurality of counters, each of the first plurality of counters being operative to track a number of active cache lines associated with a corresponding one of the segments;
• and
• at least one controller operative to receive information relating to the number of active cache lines associated with the corresponding one of the segments from the first plurality of counters and to implement a cache segment replacement policy for determining which of the plurality of segments to replace as a function of at least the information relating to the number of active cache lines associated with the corresponding one of the segments.

An apparatus for performing data caching, comprising:

• at least a first memory organized into a plurality of segments, at least a portion of the memory address including a segment identifier referencing one of the plurality of segments;
• at least a second memory including a subset of the plurality of segments included in the first memory;
• and
• at least one processor coupled with the first memory and the second memory, the at least one processor being operative:
• (i) to receive a main memory address for accessing requested data in a corresponding location in the first memory;
• (ii) to compare segment identifiers corresponding to a plurality of segments in the second memory with the segment identifier in the received main memory address for determining whether there is a segment match;
• (iii) for each of at least a subset of the plurality of segments, to track a number of active cache lines in a cache memory associated with a corresponding one of the segments;
• and (iv) when a segment match has not occurred and the cache memory is full, to implement a cache segment replacement policy based at least on information relating to the number of active cache lines associated with the corresponding one of the segments.