Load store unit with load miss result buffer

A system for reading data with a plurality of load instructions from a memory system having a level one cache and a level two memory sub-system, comprising:

• means for storing a first missed load instruction in a primary entry of an outstanding load miss buffer;
• means for storing a first data unit requested by the first missed load instruction in a load miss result buffer;
• means for storing a second missed load instruction in a dependent entry the outstanding load miss buffer in response to a determination that the second missed load instruction requests a same cache line as the first missed load instruction, wherein the dependent entry is associated with the primary entry;
• means for storing a second data unit requested by the second missed load instruction in the load miss result buffer;
• means for reading the first data unit from the load miss result buffer for the first missed load instruction in response to the first missed load instruction being re-issued;
• and
• means for reading the second data unit from the load miss result buffer for the second missed load instruction in response to the second missed load instruction being re-issued.

A load store unit configured to retrieve data from a memory system having a level one cache and a level two memory sub-system, comprising:

• a load scheduler configured to issue load instructions;
• a load pipeline coupled to the load scheduler and configured to execute the load instructions;
• an outstanding load miss buffer coupled to the load pipeline and configured to store missed load instructions, wherein the outstanding load miss buffer comprises multiple sets of related entries and is configured to store a subset of the missed load instructions that request a same memory address in entries of one of the sets of related entries;
• and
• a load miss result buffer coupled to the load pipeline and configured to store data units for the missed load instructions,
• wherein the load pipeline is configured to retrieve a first data unit, of the data units, from the load miss result buffer in response to a first missed load instruction being re-issued from the outstanding load miss buffer.