Information processing device, memory access control device, and address generation method thereof
AssigneeNEC Corporation
InventorYasuhiro Nishigaki
Life of this patent
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Abstract
An information processing device according to the present invention includes an operation unit that outputs an access request, a storage unit including a plurality of connection ports and a plurality of memories capable of a simultaneous parallel process that has an access unit of a plurality of word lengths for the connection ports, and a memory access control unit that distributes a plurality access addresses corresponding to the access request received for each processing cycle from the operation unit, and generates an address in a port including a discontinuous word by one access unit for each of the connection ports.
Claims10
An information processing device comprising:
- an operation unit configured to process one-word-length data per processing cycle, and to output an access request in synchronization with the processing cycle;
- a storage unit comprising a plurality of connection ports and a plurality of memories configured to perform input/output processing with respect to the plurality of connection ports in a simultaneous parallel process,
- wherein data with a plurality of word lengths act as an access unit for each of the connection ports;
- and
- a memory access control unit configured to distribute, for each processing cycle, a plurality of access addresses corresponding to the access request received from the operation unit, and to generate an address in a port, including a spatially discontinuous word, utilizing one access unit for each of the connection ports.
An apparatus, comprising:
- an operation unit configured to process one-word-length data per processing cycle, and to output an access request in synchronization with the processing cycle, and
- a storage unit including a plurality of connection ports and a plurality of memories configured to perform input/output processing with respect to the plurality of connection ports in a simultaneous parallel process, and configured to generate an address in a port for each of the connection ports of the storage unit based on the access request between the operation unit and the storage unit, wherein data with a plurality of word lengths act as an access unit for each of the connection ports,
- a routing address generation unit configured to generate a routing address for specifying the connection port to assign each of a plurality of access addresses corresponding to the access request;
- a conflict arbitration unit configured to perform conflict arbitration of the connection port to assign the access address based on the routing address;
- an address in port generation unit configured to generate the address in the port based on the access address input in a plurality of processing cycles of the memory access control device;
- and
- a crossbar unit configured to assign the address in the port to one of the plurality of connection ports according to a conflict arbitration process of the conflict arbitration unit.
An address generation method in an information processing device including:
- outputting, with an operation unit configured to process one-word-length data per processing cycle, an access request in synchronization with the processing cycle;
- using a plurality of memories to perform input/output processing with respect to a plurality of connection ports of a storage unit, in a simultaneous parallel process, wherein data with a plurality of word lengths act as an access unit for each of the connection ports;
- generating the plurality of access addresses corresponding to the access request for each processing cycle of the operation unit;
- and
- distributing the plurality of access addresses into the plurality of connection ports, and generating an address in a port including a spatially discontinuous word belonging to a different processing cycle of the operation unit, utilizing one access unit for each of the connection ports.
Dependencies are inferred from the claim text.