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US 8,806,131 B2Granted
Multi-serial interface stacked-die memory architecture
AssigneeMicron Technology, Inc.
InventorsJoe M. Jeddeloh, Paul A. LaBerge
Life of this patent
Estimating the term…
Abstract
Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.
Claims19
A memory system comprising:
- a memory vault;
- a memory vault controller configured to communicate with the memory vault;
- a communication link interface configured to communicatively couple the memory vault controller at least one of an originating device or a destination device;
- a switch configured to connect the communication link interface to the memory vault controller;
- a packet decoder coupled to the switch to receive an outbound packet sent from the originating device across an outbound of the communication link interface, to extract at least one of an outbound memory command, an outbound memory address, or an outbound memory data field from the outbound packet, and to present a set of select signals to the switch;
- and
- a packet encoder coupled to the switch to receive at least one of an inbound memory command, an inbound memory address, or inbound memory data from the memory vault controller, and to encode the inbound memory address or the inbound memory data into an inbound packet for transmission across an inbound of the communication link interface to the destination device, wherein the communication link interface includes:
- a differential pair serial path coupled to the originating device;
- a deserializer coupled to the differential pair serial path;
- and
- a demultiplexer communicatively coupled to the deserializer.
8 more elements
A memory system comprising:
- a memory vault;
- a memory vault controller configured to communicate with the memory vault;
- a communication link interface configured to communicatively couple the memory vault controller at least one of an originating device or a destination device;
- a switch configured to connect the communication link interface to the memory vault controller;
- a packet decoder coupled to the switch to receive an outbound packet sent from the originating device across an outbound of the communication link interface, to extract at least one of an outbound memory command, an outbound memory address, or an outbound memory data field from the outbound packet, and to present a set of select signals to the switch;
- and
- a packet encoder coupled to the switch to receive at least one of an inbound memory command, an inbound memory address, or inbound memory data from the memory vault controller, and to encode the inbound memory address or the inbound memory data into an inbound packet for transmission across an inbound of the communication link interface to the destination device;
- an additional memory vault and an additional memory vault controller coupled to the additional memory vault and the communication link interface;
- a control register coupled to the switch to accept configuration parameters from a configuration source and to configure the switch to operate according to a selectable mode, wherein the selectable mode includes at least one of operating the memory vault and the additional memory vault synchronously in response to at least one request or operating the memory vault and the additional memory vault asynchronously in response to at least one request.
6 more elements
A memory system comprising:
- a memory vault;
- a memory vault controller coupled to the memory vault;
- and
- a communication link interface configured to couple the memory vault controller at least one of an originating device or a destination device, wherein the communication link interface includes a differential pair serial path coupled to the originating device, a deserializer coupled to the differential pair serial path, and a demultiplexer communicatively coupled to the deserializer, the memory vault controller including:
- a programmable vault control logic component to generate at least one of bank control signals or timing signals associated with the memory vault;
- a memory sequencer coupled to the programmable vault control logic to perform at least one of command decode operations, memory address multiplexing operations, memory address demultiplexing operations, memory refresh operations, memory vault training operations, or memory vault prefetch operations associated with the corresponding memory vault;
- a first buffer coupled to the programmable vault control logic to buffer data arriving at the memory vault controller from the originating device;
- and
- a second buffer coupled to the programmable vault control logic to buffer data arriving at the memory vault controller from the memory vault.
6 more elements
A method comprising:
- creating inbound data streams from command, address, or data read from a memory vault;
- switching the inbound data streams to a communication link interface;
- transferring the inbound data streams across the communication link interface to a device, the communication link interface including a differential pair serial path coupled to the device, a deserializer coupled to the differential pair serial path, and a demultiplexer communicatively coupled to the deserializer;
- accessing an inbound data word from the memory vault;
- switching the inbound data word to a packet encoder associated with the communication link interface;
- packetizing the inbound data word into an inbound packet;
- segmenting the inbound packet into inbound sub-packets;
- and
- sending the inbound sub-packets to a multiplexer.
6 more elements
Dependencies are inferred from the claim text.