Memory access device outputting transfer request
AssigneeFujitsu Semiconductor Limited
InventorsShigeyasu Murase, Ayuko Uchida, Akio Kanzaki
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AssigneeFujitsu Semiconductor Limited
InventorsShigeyasu Murase, Ayuko Uchida, Akio Kanzaki
Estimating the term…
A memory access device includes a second memory coupled between a processor and a first memory; a memory controller configured to transfer a data from the first memory to the second memory based on a transfer request; a read controller configured to read the data from the second memory, output the data to the processor, and control a read pointer indicating an address reading the data from the second memory; and a write controller configured to output the transfer request to the memory controller, wherein the write controller computes an available capacity of the second memory based on the read pointer, a size of the second memory and a cumulative addition value obtained by adding cumulatively a size of the data which is requested from the processor, and outputs the transfer request based on the available capacity.
A memory access device configured to perform data transfer between a processor and a first memory, the memory access device comprising:
A memory access system, comprising:
A processing method of a memory access device configured to perform data transfer between a processor and a first memory, the processing method comprising:
Dependencies are inferred from the claim text.