Adaptive FIFO
AssigneeSanDisk Technologies LLC
InventorSharon Mutchnik
Life of this patent
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Abstract
An adaptive synchronous FIFO includes a plurality of input data latch stages that sample variable-length input data at a write clock frequency, and a data compression circuit that combines the variable-length input data, together with partial-row data from a row of the FIFO storage array, and writes the combined data at a read clock frequency. The number of data latch stages is adaptive according to the ratio of the read and write clock frequencies.
Claims19
A method of operating a synchronous First-In, First-Out (FIFO) circuit, with variable-length data, comprising:
- receiving variable-length data from an input;
- reading partial-row data from a partially-filled row of a FIFO storage array;
- appending the received variable-length data to the partial-row data;
- and
- storing the partial-row data, together with at least a first portion of the appended received variable-length data, in a first row of the FIFO storage array.
A method of operating a synchronous First-In, First-Out (FIFO) circuit, at a fraction of a write clock speed, comprising:
- receiving an input at the write clock speed (WCLK);
- sampling the input in N latches, where N is an integer that is greater than 1, each of the N latches sampling every N clock cycles;
- combining the contents of the N latches at a read clock speed (RCLK), the read clock speed given by:
- RCLK=WCLK/N;
- storing the combined contents of the N latches in a storage array at the read clock speed;
- and
- reading the storage array at the read clock speed.
A synchronous First-In, First-Out (FIFO) circuit with variable clock ratio, comprising:
- NHW input latch stages for receiving variable-length data, where NHW>1;
- a FIFO storage array;
- and
- a data compression circuit that combines partial-row data from a row in the FIFO storage array with variable-length data from NConfig of the NHW input latch stages prior to storing the combined partial-row data and the variable-length data together in the FIFO storage array.
A synchronous First-In, First-Out (FIFO) circuit for variable-length data, comprising:
- a FIFO storage array;
- an input latching unit for receiving variable-length data;
- and
- a data compression circuit that reads partial-row data from a partially filled row of the FIFO storage array, appends variable-length data from the input latching unit, and stores the partial-row data, together with at least a first portion of the appended variable-length data, in a first row of the FIFO storage array.
Dependencies are inferred from the claim text.