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US 8,806,109 B2Granted
Protection of secret keys
AssigneeSTMicroelectronics (Rousset) SAS
InventorSylvie Wuidart
Life of this patent
Estimating the term…
Abstract
A method for protecting at least first data of a non-volatile memory from which the extraction of this first data is triggered by the reading or the writing, by a processor from or into the memory, of second data independent from the first data, said first data being provided to a circuit which the processor cannot access.
Claims23
A method for protecting data stored in a first memory area of a non-volatile memory, the method comprising acts of:
- in response to the processor issuing a memory access request in read or write mode, the memory access request comprising at least one second memory address in the non-volatile memory, the at least one second memory address in a second memory area different from the first memory area, using the at least one second memory address to calculate at least one first memory address in the first memory area;
- extracting from the non-volatile memory first data stored at the at least one first memory address;
- and
- providing the extracted first data to a circuit to be stored in one or more internal registers of the circuit, wherein the one or more internal registers of the circuit are inaccessible to the processor, and wherein the first data is provided to the circuit via a selector connected on the one hand to at least one data bus and on the other hand to the circuit.
1 more element
An integrated circuit comprising:
- a processor;
- at least one data bus and an address bus accessible by said processor, the at least one data bus and the address bus being connected to at least one program memory and a non-volatile memory;
- and
- the non-volatile memory connected to the at least one data bus and the address bus, wherein the non-volatile memory is, at a data output, associated with a selector connected on the one hand to the at least one data bus and on the other hand to a logic circuit that is inaccessible to the processor, wherein the non-volatile memory is configured to:
- in response to the processor issuing a memory access request in read or write mode, the memory access request comprising at least one second memory address in the non-volatile memory, provide first data to the logic circuit, wherein the first data is extracted from at least one first memory address in the non-volatile memory, the at least one first memory address being calculated using the at least one second memory address, and wherein the first data is to be stored in one or more internal registers of the logic circuit that are inaccessible to the processor.
2 more elements
A system comprising:
- an integrated circuit comprising:
- a processor;
- and
- a non-volatile memory that is associated with a selector connected to at least one data bus and to a logic circuit that is inaccessible to the processor, wherein the non-volatile memory is configured to:
- in response to the processor issuing a memory access request in read or write mode, the memory access request comprising at least one second memory address of the non-volatile memory, provide first data to the logic circuit, wherein the first data is extracted from at least one first memory address in the non-volatile memory, the at least one first memory address being calculated using the at least one second memory address, and wherein the first data is to be stored in one or more internal registers of the logic circuit that are inaccessible to the processor.
2 more elements
Dependencies are inferred from the claim text.