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US 8,806,071 B2Granted
Continuous read burst support at high clock rates
AssigneeSpansion LLC
InventorClifford Alan Zitlaw
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory array, an output buffer, an initial latency register, and an output signal. Often times a host device that interfaces with the memory device is clocked at high rate such that data extraction rates of the memory device are not adequate to support a gapless data transfer. The output signal is operable to stall a transmission between the memory device and the host device when data extraction rates from the memory array are not adequate to support output rates of the output buffer.
Claims20
A memory device, comprising:
- a memory array operable for storing data;
- an initial latency register operable for storing a preselected latency time;
- and
- an output buffer coupled to said memory array, wherein said output buffer stores said data prior to a transmission of said data to a host device, wherein said memory device outputs a signal to stall said transmission until said data has been stored in said output buffer, and wherein the transmission is stalled while the output signal is idle.
1 more element
An apparatus, comprising:
- a memory device operable to support continuous read bursts to a host device wherein an output signal stalls a transmission from the memory device as defined by a preselected length of time, and wherein the transmission is stalled while the output signal is idle;
- a bus interface providing connectivity between said memory device and said host device;
- and
- a processor.
1 more element
A method, comprising:
- requesting data from a memory device on a computer system, wherein said memory device comprises an initial latency register storing a preselected latency time;
- retrieving a page or partial page of said data from an array within said memory device;
- holding an output signal idle until page or partial page of data is stored into an output buffer and placed on a data bus;
- and
- toggling said output signal while transmitting said page or partial page of data to a host device to indicate to said host device that said page or partial page of data is available on said data bus, and wherein the data transmission is stalled while the output signal is idle.
2 more elements
Dependencies are inferred from the claim text.