Parallel redundant decimal fused-multiply-add circuit

A method for performing a floating-point fused-multiply-add (FMA) calculation, comprising:

• generating, by circuitry, a plurality of multiples of a multiplicand for the decimal FMA calculation, wherein the multiplicand is in a m digit binary coded decimal (BCD) format;
• generating, by circuitry, n+1 signed digits (SD) sets from a multiplier sum vector and a multiplier carry vector of a multiplier for the decimal FMA calculation;
• generating, by circuitry, a plurality of partial product vectors from the plurality of multiples of the multiplicand based on the n+1 SD sets and a sign of the FMA calculation;
• and
• adding the plurality of partial product vectors and an addend for the FMA calculation to generate a result sum vector and a result carry vector in a m+n digit BCD format,
• wherein m and n are integers, and
• wherein the FMA calculation comprises a calculation of a×b±c, where a represents the multiplicand, b represents the multiplier, c represents the addend, × represents a multiplication operator, and ± represents one of an addition operator and a subtraction operator.

A non-transitory computer-readable medium storing a description expressed in a hardware description language which is interpreted by a computer to specify a circuit comprising:

• a partial product generation module comprising:
• a multiples generator unit configured to generate a plurality of multiples of a multiplicand for the decimal FMA calculation, wherein the multiplicand is in a m digit binary coded decimal (BCD) format;
• a recoding unit configured to generate n+1 signed digits (SD) sets from a multiplier sum vector and a multiplier carry vector of a multiplier for the decimal FMA calculation;
• and
• a multiples selection unit configured to generate a plurality of partial product vectors from the plurality of multiples of the multiplicand based on the n+1 SD sets and a sign of the FMA calculation;
• and
• a carry save adder (CSA) tree coupled to the partial product generation unit and configured to add the plurality of partial product vectors and an addend for the FMA calculation to generate a result sum vector and a result carry vector in a m+n digit BCD format,
• wherein m and n are integers, and
• wherein the FMA calculation comprises a calculation of a×b±c, where a represents the multiplicand, b represents the multiplier, c represents the addend, × represents a multiplication operator, and ± represents one of an addition operator and a subtraction operator.