Fused multiply-add apparatus and method

A fused multiply-add (FMA) method comprising:

• generating a partial sum and a partial carry by dividing each of the mantissas of first and second floating-point numbers into a plurality of n-bit segments, computing partial products of the n-bit segments, and adding up the computed partial products;
• determining whether the mantissa of a third floating-point number is zero;
• and
• if the mantissa of the third floating-point number is zero,
• generating a partial sum that has a first bit size and a partial carry that has the first bit size by adding the partial sum and the partial carry to the LSBs of the mantissa of the third floating-point number,
• extending the MSBs of the mantissa of the third floating-point number, and
• generating a mantissa that has a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to the extended MSBs,
• wherein the generating of the partial sum and the partial carry, and the generating of the mantissa that has the second bit size are performed at a processor.

A fused multiply-add (FMA) apparatus comprising:

• a partial product generator configured to generate a partial product and a partial carry based on a mantissa of a first floating-point number and a mantissa of the second floating-point number;
• a carry save adder configured to add the partial sum and the partial carry to one or more least significant bits (LSBs) of a third floating-point number to generate a first bit-size partial sum and a first bit-size partial carry;
• a carry select adder configured to add the partial sum and partial carry to one or more most significant bits (MSBs) of the third floating point number or adds the first bit-size partial carry and the first bit-size partial sum to the one more MSBs of the third floating-point number, to generate a second bit-size partial sum and a second bit-size partial carry;
• a storage configured to temporarily store the second bit-size partial sum and the second bit-size partial carry;
• and
• a selector configured to receive a signal that indicates whether the LSBs of the third floating-point number are zero, and determine whether to transmit the partial sum and the partial carry to the carry save adder or the carry select adder based on the received signal.