US 8,805,910 B2Granted

System and method for generating discrete-time model (DTM) of continuous-time model (CTM) for a dynamical system

AssigneeKylowave Inc.

InventorsJulio C. G. Pimentel, Emad Gad

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Abstract

Method and apparatus for processing continuous-time models (CTM) in a digital processing architecture is disclosed. The discrete state-space technique maps the CTM into the discrete-time model (DTM) and stores the states of the system in a sample time independent discrete state space set of matrices. The resulting state-space matrices can be processed in software or directly in hardware. The method disclosed is particularly suited to be used in automatic synthesis algorithms where a digital circuit is generated from an algorithm described in a high level language or model representation such as, for example, data flow or bond graph into a hardware description language (HDL), and the HDL model can be synthesized using system specific tools to generate an application specific integrated circuit (ASIC) or an FPGA configuration.

Claims29

Dependent claims

A method for execution by a processor, the method comprising:

retrieving from the memory a continuous time model (CTM) defining a continuous-time electrical or mechanical system;
determining a sampling time and CTM state-space matrices [A, B, C, D] for the CTM defined for a dynamical system ordinary differential equation mathematical formulation;
determining an order of approximation [i,j,k] parameters of the coefficients of an Obreshkov integration formula, to be used in determining a discrete time model (DTM) [Adm, Bdm, Cdm, Ddm] to provide an approximation of accuracy and to meet A- or L-stability requirements defined for the dynamical system;
and
discretizing the CTM into the DTM using the selected order of approximation [i,j,k], and the CTM state-space matrices [A, B, C, D] and sampling time (T) by calculating Obreshkov-coefficient and matrices [Adm, Bdm, Cdm, Ddm] using Obreshkov-based polynomial matrices;
and
storing the DTM representing the continuous-time electrical or mechanical system to the memory;
wherein subscript d in the state-space matrix refers to a matrix for the DTM and m subscript refers to the parameter k of the order of the discretization such that 0<=m<=k and the DTM is a fixed point or a floating point representation.

5 more elements

An apparatus the apparatus comprising:

a processor for executing instructions stored in a memory coupled to the processor, the instructions for performing:
retrieving from the memory a continuous time model (CTM) defining a continuous-time electrical or mechanical system;
receiving a discrete time model (DTM) output and determining a sampling time (T) and CTM state-space matrices [A, B, C, D] defined for a dynamical system ordinary differential equation mathematical formulation;
determining an order of approximation [i,j,k] parameters of the coefficients of an Obreshkov integration formula, to be used in determining the DTM [Adm, Bdm, Cdm, Ddm] to provide an approximation of accuracy and to meet A- or L-stability requirements defined for the dynamical system;
discretizing the CTM into a DTM using the selected order of approximation [i,j,k], and the CTM state-space matrices [A, B, C, D] and sampling time by calculating Obreshkov coefficients and matrices [Adm, Bdm, Cdm, Ddm] using Obreshkov polynomial matrices;
and
storing the DTM representing the continuous-time electrical or mechanical system to the memory;
wherein subscript d in the state-space matrix refers to a matrix for the DTM and m subscript refers to the parameter k of the order of the discretization such that 0<=m<=k and the DTM is a fixed point or a floating point representation.

5 more elements

An apparatus for executing a discrete time model (DTM) the apparatus comprising:

a processor coupled to a memory, the memory containing instructions which when executed by the processor performing:
retrieving from the memory a continuous time model (CTM) defining a continuous-time electrical or mechanical system;
computing an approximation for output signals y (nT) at the sampling time (T) comprising:
wm(n+1,T)=Admwm(n,T)+Bdmu(n,T)
x*m(n,T)=Cdmwm(n,T)+Ddmu(n,T)
where a DTM output is defined by:
Y
⁡
(
z
)
:=
DU
⁡
(
z
)
+
C
⁢
∑
m
=
0
k
⁢
⁢
X
m
*
⁡
(
z
)
or equivalently
y
⁡
(
n
,
T
)
:=
Du
⁡
(
n
,
T
)
+
∑
m
=
0
k
⁢
⁢
x
m
*
⁡
(
n
,
T
)
where Y(z), U(z), X*m(z) are the Z-transform of an equivalent y(n,t), u(n,t),x*m(n,t)
using DTMs defined by [Adm, Bdm, Cdm, Ddm] for the CTM discretized using a selected order of approximation [i,j,k], and CTM state-space matrices [A, B, C, D] and a sampling time by calculated by Onreshkov coefficient and matrices [Adm, Bdm, Cdm, Ddm] using Obreshkov-based polynomial matrices where wm is an auxiliary state variable, n is the timestep number, z is the z-transform variable and xm is the dynamical system state variable;
and
storing the DTMs representing the continuous-time electrical or mechanical system to the memory,
wherein the DTMs are fixed point or floating point representations and the Obreshkov-based polynomial matrices [Lm, Hm] and [Qm,Gm] are defined by:
⁢
H
m
⁡
(
AT
)
:=
∑
k
=
m
i
⁢
⁢
(
-
1
)
k
⁢
α
j
,
i
,
k
⁡
(
AT
)
k
-
m
;
⁢
L
m
⁡
(
AT
)
:=
∑
k
=
m
i
⁢
⁢
α
i
,
j
,
k
⁡
(
AT
)
k
-
m
;
⁢
G
m
⁡
(
AT
)
=
∑
k
=
0
m
-
1
⁢
α
j
,
i
,
k
⁡
(
AT
)
k
+
(
AT
)
m
⁢
H
m
⁡
(
AT
)
;
⁢
and
Q
m
⁡
(
AT
)
=
∑
k
=
0
m
-
1
⁢
-
α
i
,
j
,
k
⁡
(
AT
)
k
+
∑
k
=
0
m
-
1
⁢
⁢
(
-
1
)
k
⁢
α
j
,
i
,
k
⁢
L
m
⁡
(
AT
)
⁢
H
m
-
1
⁡
(
AT
)
⁢
(
AT
)
k
the discretizing the CTM into the DTM further comprises:
determining [Adm, Bdm, Cdm, Ddm] where
Adm=Lm(AT)Hm−1(AT)−Qm(AT)Gm−1(AT)
Bdm=Qm(AT)Gm−1(AT)Hm(AT)(BT
Cdm=Gm−1(AT)
Ddm=−Gm−1(AT)Hm(AT)(BT).

251 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/040,624Filed 4 Mar 2011
Published: US 2012/0226726 A16 Sep 2012
Granted: 12 Aug 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 30/343
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: logical level
G05B 17/02
Systems involving the use of models or simulators of said systems: electric
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/3312
Using simulation: timing analysis