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US 8,805,905 B2Granted
On-line randomness test for restart random number generators
AssigneeSeagate Technology LLC
InventorLaszlo Hars
Life of this patent
Estimating the term…
Abstract
An apparatus includes a first counter for counting successive bits representative of a logic 1, and a second counter for counting successive bits representative of a logic 0, wherein a first predetermined count on the first counter or a second predetermined count on the second counter indicates a randomness failure. A method for testing randomness performed by the apparatus is also included.
Claims20
An apparatus comprising:
- a first counter circuit for receiving a series of bits from a random number generator and for counting successive bits in the series of bits representative of a logic 1;
- a second counter circuit for counting successive bits in the series of bits representative of a logic 0;
- wherein the first counter circuit is reset when a received bit in the series of bits is a logic 0, and the second counter circuit is reset when a received bit in the series of bits is a logic 1;
- and
- wherein a first predetermined count on the first counter circuit or a second predetermined count on the second counter circuit indicates a randomness failure.
2 more elements
A method comprising:
- receiving a sequence of bits representing a plurality of logic 1's and 0's;
- using a first counter circuit to count successive bits representative of a logic 1;
- using a second counter circuit to count the bits representative of a logic 0;
- resetting the first counter circuit when a received bit is a logic 0;
- resetting the second counter circuit when a received bit is a logic 1;
- producing a failure indication when the first counter circuit reaches a first predetermined count;
- and
- producing a failure indication when the second counter circuit reaches a second predetermined count.
5 more elements
A device comprising:
- a first counter circuit adapted to:
- receive a series of bits;
- count successive bits representative of a logic 1 in the series of bits, producing a count of successive ones;
- reset the count of successive ones in response to a bit in the series of bits being a logic 0;
- a second counter circuit adapted to:
- receive the series of bits;
- count successive bits representative of a logic 0 in the series of bits, producing a count of successive zeros;
- reset the count of successive zeros in response to a bit in the series of bits being a logic 1.
5 more elements
Dependencies are inferred from the claim text.